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Google Silicon Digital Design Engineer III 
United States, California, Mountain View 
41452367

20.02.2025
Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
  • Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.

Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience with Application-Specific Integrated Circuit (ASIC) design methodologies for clock domain checks, reset checks and low power design.
  • Experience in ASIC design flows and methodologies.
  • Knowledge in one of these areas: Processor Cores, Buses/Fabric/NoC, Debug/Trace, Interrupts or Clocks/Reset.
  • Knowledge of high performance and energy efficient design techniques.
  • Knowledge of ASIC Verification or Design for testing (DFT).