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Google Staff ASIC Design Verification Engineer Platforms Devices United States, California, Mountain View 378074094
14.10.2025
Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience in taking multiple silicon projects from concept to product release.
- Experience strategizing and verifying digital logic at RTL and GLS level using SystemVerilog or C/C++ or Universal Verification Methodology (UVM).
- Experience with system-level architecture, scripting languages, Software (SW) development frameworks and their impact on Design Verification (DV).
- Experience creating and using verification components and environments in standard verification methodology from scratch through Tapeout.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 12 years of experience with building verification methodologies that span simulation, formal, emulation and FPGA prototyping.
- Experience with Interconnect Protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL).
- Experience with performance verification of SOCs, pre-Silicon analysis and post-Silicon correlation.
- Experience verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).
- Experience with architectural background in one or more of: Caches Hierarchies, Coherency, Memory Consistency Models, DDR/LPDDR, PCIe, Packet Processors, Security, Clock and Power Controllers.
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