Intel Senior CPU Subsystem Design Engineer 

United States, California, San Jose 

362833963

In this role, the successful incumbent will provide the following but not limited to:

• Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design.

• Participates in the definition of architecture and microarchitecture features of the block being designed.

• Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence.

• Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.

• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

• Follows secure development practices to address the security threat model and security objects within the design. Works with IP providers to integrate and validate IPs at the SoC level. Drives quality assurance compliance for smooth IPSoC handoff.

• Works with Physical Design teams to synthesize their RTL block and provide estimates of timing, area and power.

Candidate must possess the minimum qualifications below to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Bachelor's degree in computer engineering, electrical Engineering or related field.

Minimum Qualifications

• 10+ years of relevant experience in the following areas:

• Experience with CPU based SoC designs processor based SoC architectures.

• Experience with NoC design and integration with AMBA interconnect protocols

• Working experience with peripheral IPs such as USB, Ethernet, I3C.

• RTL developer using ASIC development techniques and designs flows at modern technology nodes including synthesis and timing closure

• Experience in designing clock circuitry, debug, security, low power methodologies at the SoC level.

• Digital Design experience

• Experience with scripting languages (e.g., Python or Perl).

Preferred Requirements:

• Master's degree in computer engineering, Electrical Engineering or related field.

• 6+ years of experience in the following areas:

• Digital design involving multiple clock domains and clock, power management. Low power design, tools and methodologies. Power intent UPF specifications.

• Experience with Ethernet, PCIe or TSN.

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing BenefitsAnnual Salary Range for jobs which could be performed in US, California: $162,041.00-$259,425.00
*Salary range dependent on a number of factors including location and experience