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Apple Graphics FE Implementation Engineer United States, Texas, Austin 332846479
06.06.2024
Description
You will be responsible for PPA optimization of the netlist, working closely with the RTL and Physical design teams. You will also deliver key netlist quality achievements for your partition and be involved in understanding and improving our current methodologies. Through this collaboration, you will deliver the best-in-class GPU’s for the best consumer products. If you’re ready to help chart the future of Apple Silicon, we’d love to talk to you.
Key Qualifications
- We are looking for candidates with experience with physical synthesis, including logic and PPA optimization techniques.
- Understanding and application of physical design and static timing analysis principles.
- Proficient in Verilog and/or System Verilog and scripting languages.
- Ability to analyze critical paths and guide RTL designs to optimal solutions.
- Experience using logic equivalence tools for RTL and Gate-level designs.
- Collaborate effectively with IP teams spanning multiple sites.
- Preferred, but not required:
- Familiarity with DFT insertion.
- Familiarity with reset domain, multi-clock domain, multi-power domain (UPF), linting tools and concepts across RTL and Gate-Level.
- Experience implementing ECOs for functionality and timing.
Education & Experience
We are looking for candidates with BS + 3 years of relevant experience.
Additional Requirements
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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