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Apple Graphics FE Implementation Engineer United States, Texas, Austin 210105620
06.06.2024
Description
You will be responsible for RTL to netlist generation working closely with the RTL and Physical design teams. You will also deliver key netlist quality achievements for your partition, engage in Lint, CDC, Logic equivalence checks and support ECO generation activities. Through this collaboration, you will deliver the best-in-class GPU’s for the best consumer products. If you’re ready to help chart the future of Apple Silicon, we’d love to talk to you.
Key Qualifications
- We are looking for candidates with relevant coursework in Computer Architecture, Digital Logic Design and CMOS VLSI design.
- Understanding of CMOS device characteristics for area/timing/power tradeoffs.
- Ability to read and understand Verilog and System Verilog.
- Knowledge of static timing analysis concepts (setup and hold timing) and metastability concerns.
- Proficient in at least one scripting language.
- Ability to work with multiple teams across different sites.
- Preferred, but not required:
- Exposure to industry standard rtl2gds tools for synthesis, place and route, static timing analysis.
- Exposure to Clock/Reset domain crossing principles.
- Familiarity with DFT methodologies.
Education & Experience
We are looking for candidates with BS + 0 years of relevant experience.
Additional Requirements
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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