Microsoft Principal Physical Design Engineer 

United States, Texas, Austin 

328870512

Microsoft Silicon, Cloud, Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission.

As Microsoft's cloud business continues to grow the ability to develop new generation silicon is of paramount importance. To achieve this goal, Microsoft’s Cloud Compute Development Organization (CCDO) is seeking a Physical Design (PD) CPU/High performance Intellectual Property (IP) design Lead/Engineer who is technically driven to join our silicon hardware physical design team, covering leadership, Register Transfer Level (RTL)to design ownership. We are responsible for delivering cutting-edge, High performance Central Processing Unit (CPU) & Custom Accelerator based in-house System on Chip (SOC) designs, which is instrumental in advancing Azure's server-class product roadmap. This team will be involved in numerous projects within Microsoft developing SOC silicon for Azure data centers.

to join the team.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

Required Qualifications

• 9+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
  • ORMaster's degree in Electrical Engineering, Computer Engineering, Computer Science, or related fieldAND 4+ years technical engineering experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.
• 8+ years of experience in semiconductor production design tapeouts & implementing designs through synthesis, floor-planning, place and route, extraction, timing, EMIR closure and physical verification.

Other Requirements

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

Preferred:

• Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.
• Own complete PD execution of Blocks/Partitions/Sub-systems/Sub-chips instantiating/integrating multiple other Physical partitions.
• Collaborating and influencing various aspects of PD Methodology will also be key requirement in this role.
• Own partition floorplanning for optimizing blocks for Power, Performance and Area.
• Have close collaboration with RTL team (RTL2PD liaison) to help drive and resolve design issues related to block closure.
• Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.
• Additionally influence key pieces of PD implementation methodology or specific areas such as Clocking.
• Analyzing Power, Area, and Timing (PPA) trade offs for new tech nodes & enabling project level decisions. This involves from deeper understanding of circuits, metal stack analysis, Power grid planning and other aspects which influence PPA goals.
• Partner closely with PD flow/CAD team and PD methodology team to flag & fix PD TFM issues upfront and ensure those are fixed in the next PD TFM release from CAD or are updated in the design project layer (as appropriate).
• Mentor engineers on technical aspects.
• Be fully hands-on in your individual ownerships as individual contributor and collaborate cross-team as required.
• Demonstrated expertise in coaching, collaboration, influencing, and energizing a team via effective written and verbal communication skills.
• Proven understanding of PD construction & analysis flows and methodology.
• Shown ability to execute stringent schedule, PPA targets & die size requirements.
• Effective communication, collaboration, teamwork skills and ability to contribute to diverse and inclusive teams.
• Proven track record of implementing designs through synthesis, floor-planning, place and route, extraction, timing, and physical verification.
• Understanding of constraints generation, DFT timing modes, STA analysis, Timing optimization, and Timing closure.
• Past experience with multi-voltage & power domain, multi-clock, and low power designs.
• Experience in EDA tools such as Primetime, StarRC, Cadence and/or Synopsys PnR tools etc.
• Experience and knowledge of formal equivalency checks, LP, UPF, reliability, SI, and noise analysis.
• Knowledge on ECO implementation for formality and Power/Timing convergence.

Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $137,600 - $267,000 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $180,400 - $294,000 per year.Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications and processes offers for these roles on an ongoing basis.

• Responsible for Core CPU (L1-L2) and/or non-Core/SOC Timing critical IPs’ execution with PPA (Power, Performance and Area) target accomplishments.
• Responsible for RTL to Graphic Design System methodology (GDS) implementation in Physical Design domain.
• Coordinate with CAD, RTL/Design teams, Architecture team, Power& Performance team, Technology team & other internal/external partners.
• Lead & Influence in TFM (Tools, Flows, and Methodology) & PPAS (Power, Performance, Area & Schedule) for design construction to signoff.
• Demonstrate technical expertise across various domains of Physical Design & Timing Signoff (E2E).
• Clear communications on project status & planning.
• Collaborate across various geographic locations based on need.
• Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion
• Embody our