Intel Principal Engineer Physical Design Timing 

United States, Texas 

292510095

Qualifications:

Minimum Qualifications:

• Bachelor degree in Computer Science , Computer Engineering or Electrical Engineering or related field
• 10+ years of Physical design experience with a strong understanding of digital circuits and proficiency in static timing analysis (STA) tools like PrimeTime or Innovus.
• Experience with signoff corner selection, PV guard-banding, PV convergence, including static timing and power analysis
• Strong experience in SoC and ASIC design flows on taped out designs
• Expertise in timing closure at block/chip level and ECO flows
• Experience with scripting in an interpreted language

Preferred Qualifications:

• Experience with full chip integration, die-to-die and package integration level timing signoff
• Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools
• Strong experience in CPU and GPU design flows on taped out designs
• Design tools and methods development

Experienced HireShift 1 (United States of America)US, Massachusetts, Beaver BrookUS, California, Folsom, US, Oregon, Hillsboro
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: