Nvidia ASIC Physical Design Timing Engineer 

United States, California 

193936887

What you'll be doing:

• Drive Physical Design and timing analysis and closure of NVIDIA's GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level.

• Help in driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.

• Work in a cross-functional environment interacting with multiple teams.

• Apply knowledge and experience to improve timing convergence flows working with the methodology teams.

What we need to see:

• BS (or equivalent experience) or MS (preferred) in Electrical or Computer Engineering with 2 years’ experience

• Experience with Static Timing Analysis (STA)

• Experience physical design and optimization e.g., synthesis, floorplanning, placement, CTS, routing, power, etc. is a plus

• Hands-on experience with industry standard EDA tools.

Ways to stand out from the crowd:

• Industry experience in timing convergence for ASICs, CPUs, GPUs or Network processors.

• Knowledge of deep sub-micron process nodes.

• Proficiency in AI/LLM and programming languages.