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Siemens Senior Software Engineer- High Level Synthesis 
United States, Oregon 
272701983

17.04.2025

Job Title: Senior Software Engineer – High Level Synthesis

and/or inputs and generates(RTL) code targeted for


Responsibilities

  • Continue to improve the methodology for extracting data from an ASIC PDK that is required for HLS scheduling algorithms
  • Work with RTL synthesis vendors to ensure that Catapult HLS is driving the RTL synthesis tools in the most efficient way to achieve the desired QofR goals.
  • Participate in the specification, architecture, design, and development of features.
  • Work with customers, research partners and academia to drive future innovation-related initiatives.
  • Be a force for improving development processes and product quality.
  • Work effectively with globally distributed engineering teams and the Product Validation team

Education and Experience:

  • Masters in Electrical or Computer Engineering with 8 years experience in HLS and/or RTL synthesis targeting ASICs.
  • Outstanding programming skills in C and C++ and TCL on Linux platform
  • Proficiency in memory optimization, high-performance data structures and algorithms
  • Advanced multithreading programming experience.
  • Understanding of advanced computer architectures

The Ideal Candidate should demonstrate:

  • Previous experience with product development applicable to EDA or digital design tools.
  • Solid background in object-oriented design and software engineering processes.
  • Strong analytical and problem-solving capabilities.
  • Ability to collaborate as part of globally distributed team
  • Fluency in English with strong interpersonal and excellent oral and written communication skills.

Technical Skills (Desirable) :

  • Understanding of digital design for ASIC or FPGA. Hardware architecture and tradeoffs for digital arithmetic design.
  • Working knowledge of one or more HDL languages.

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