Nvidia Senior ASIC Synthesis Engineer 

United States, Texas 

140585226

US, CA, Santa Clara

US, TX, Austin

US, CA, Remote

What You'll Be doing:

• As a Front-End ASIC Synthesis Engineer, you will own RTL synthesis and gate level optimization tasks

• Collaboration with physical design to address timing, area, congestion tradeoffs

• Drive timing closure and power/area optimization across multiple design blocks

• Work with DFT and Verification teams to ensure functional and timing correctness

What we need to see:

• BS or MS in Electrical Engineering, Computer Engineering, or equivalent experience.

• 8+ years of experience in front-end ASIC synthesis and integration.

• Deep understanding of Verilog RTL design and digital design principles.

• Proven experience with industry-standard EDA tools for synthesis (e.g., Synopsys Design Compiler).

• Hands-on experience with timing analysis, constraint management, and post-synthesis ECO flows.

• Solid background in low-power and high-performance design optimization techniques.

• Familiarity with formal verification tools (e.g., Formality/Conformal LEC) and methodologies.

Ways to stand out from the crowd:

• Knowledge of DFT/Test logic including JTAG, scan, high speed I/O loopback, and memory BIST.

• Have proficiency in programming (Python, Perl, Tcl).