Nvidia Senior ASIC Timing Engineer 

United States, Texas 

254707734

What you'll be doing:

• Drive timing analysis and closure of Nvidia’s GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level.

• Work with PD, DFX, Clocks, and other teams in coming up with timing closure strategy, creating timing constraints, driving timing and power convergence, as well as ECO implementation

• Apply knowledge and experience to improve timing convergence flows working with the methodology teams.

What we need to see:

• BS (or equivalent experience) in Electrical or Computer Engineering with 5 years experience or MS (or equivalent experience) with 2 years experience in Timing and STA

• Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation and management.

• Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis.

• Expertise and in-depth knowledge of industry standard STA and timing convergence tools.

• Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes.

Ways to stand out from the crowd:

• Background in domain specific STA and timing convergence, such as GPUs, CPUs, DPUs/Network processors, or SOCs

• Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan, BIST, etc.

• Understanding and timing closure of digital logic/macros in AMS designs/IPs.

• Experience in methodology and/or flow development as well as automation.