Cisco Senior ASIC Timing Engineer 

United States, Georgia, Atlanta 

156883803

The application window is expected to close on 8/25/25.

Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

This is a senior contributor role focused on delivering highly-complex ASICS in advanced technology nodes that are used in next generation telecom systems. The role involves detailed running timing analysis and driving timing closure at the full-chip level. This includes providing ECO scripts and guidance to designers for delivering tape-out quality for all parts of the design, in a highly team focused environment.

• Involves in static timing analysis (STA) methodology and flow. Including but not limited to latest timing technologies, like latest on-chip variation modeling techniques, PVT selection, extraction methodology and flow, etc.
• Run signoff timing analysis at the top level, drive closure of timing across the team. Interface with EDA vendors on issues/features/enhancements on timing tools.
• Work closely with RTL designers to debug and root-cause timing issues related to design, tools, etc. and arrive at a feasible solution through the augmentation of input and design collateral.

• Bachelor’s Degree in electrical engineering with 12 + years, or MS degree with 8 + years, or a PhD with 5+ year of experience
• Experience in advanced technology nodes 16nm and below
• Experience with industry standard CAD methodologies from Cadence, Synopsys and/or Mentor
• Experience with scripting skills such as TCL, Perl, or Python.
• Experience executing ASICs from product definition to production release.

• Experience with FinFET technologies
• Experience with DSP algorithms
• Experience in telecom design space
• Experience presenting technical information to technical and non-technical audience