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Apple Graphics FE Implementation Engineer United States, California 224911721
14.04.2025
- Experience with physical synthesis, including logic and PPA optimization techniques
- Experience with Verilog, System Verilog or other scripting languages
- Experience using logic equivalence tools for RTL and Gate-level designs
- BS + 3 years of relevant experience
- Understanding and application of physical design (PD) and static timing analysis (STA) principles
- Ability to analyze critical paths and guide RTL designs to optimal solutions
- Collaborate effectively with IP teams spanning multiple sites
- Familiarity with DFT insertion
- Familiarity with reset domain, multi-clock domain, multi-power domain (UPF), linting tools and concepts across RTL and Gate-Level
- Experience implementing ECOs for functionality and timing
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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