Microsoft Senior Logic Design Engineer 

United States, California, Mountain View 

213209221

Required Qualifications:

• 7+ years of related technical engineering experience

• OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience

• OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience

• OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

• 4+ years experience in high-speed digital logic design including microarchitecture specification development, RTL coding in Verilog/System Verilog, design verification collaboration, and CDC/Lint closure

• 4+ years of experience in synthesis, floorplanning, timing constraints, power / performance / area (PPA) trade-offs, and post-silicon debug

• Experience in one or more of the following:

• High-performance memory subsystems and multi-level caches

• System knowledge (software/firmware/hardware interactions and optimization)

• High-throughput processor design

• Industry-standard bus interfaces such as the Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) protocols

• Fixed and floating-point arithmetic datapath design and optimization

• Fabric and interconnect

Other Requirements:

, customer and/or government security screening requirementsfor this role. These requirements include but are not limited to the Microsoft Cloud Background Check: This position will beto pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• 10+ years of industry experience in logic design delivering complex solutions.

• SuccessfulApplication-Specific Integrated Circuit(ASIC) tape outs in deep sub-micron technologies.

• Scripting language such as Python or Perl.

• Good background in debugging designs as well as simulation environment.

• Knowledge of verification principles, testbenches, Universal Verification Methodology (UVM), and coverage.

• Experience working on Artificial Intelligence (AI) / Machine Learning (ML) SoCs.

• Working knowledge of writing assertions, coverage, and formal verification.

• Effective communication skills, self-motivation, and ability to collaborate with larger teams within Microsoft.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until Aug 2, 2024.

• Establish yourself as an integral member of a digital logic design team for the development of AI components with focus on micro-architectural based functions and features.
• Be responsible for
  • Logic design/Register Transfer Level (RTL) entry
  • Design quality, including: Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), power etc.
  • Timing closure of high-performance digital Intellectual Property (IP)
  • Silicon validation
• Collaborate with the verification team to ensure the implementation meets both architectural and micro-architectural intent.
• Interface witharchitecture,physical design (PD), design for test(DFT), and other teams tooptimizetradeoffs within the design.
• Provide technical leadership through mentorship and teamwork.
• Other
• Embody our and