Broadcom R&D Engineer 

United States, California, San Jose 

206151349

Key Qualifications

• Broad knowledge of advanced silicon and packaging process technologies

• Working knowledge of the Advanced Semiconductor Technology nodes including FinFET and Gate All Around technology; Design experience is a plus

• Working knowledge of 2.5D packaging technology and 3D stacked IC

• Knowledge and use of various EDA offerings from major EDA suppliers in semiconductor industry for IP and chip design

• Working knowledge of IP and chip design flow for analog and digital

• Experience with parametric and yield data analysis. Proficiency with statistical data analysis tools

• Experience with usage of device model usage, layout and circuit simulation tools, Parasitic extraction and simulation, abstract and LEF/DEF generation, LVS/ERC checks, physical verification

• Conducting design reviews & creating slides and other associated documentation

• Assisting with integration of IP into SOCs and creating guidelines

• Experience with yield failure mechanisms and tools for root cause finding (EFA, PFA); Familiarity with device reliability degradation mechanisms, test methods, and lifetime modeling

• Exceptional data analysis, problem solving, and interpersonal skills

• Being able to work with large teams from manufacturing, technology and packaging

Job Description

• Provide design support for IP & ASIC to create robust designs in line with advanced semiconductor and packaging process flows & constraints

• Work closely with technology experts and Silicon manufacturing teams to deploy the technology requirements for ASIC product design & design automation flows

• Define process flows, design rules and IP adaptation guidelines for the advanced semiconductor technology and advanced packaging technology

• Define technology test vehicles for advanced technology & packaging for validation before product manufacturing

• Provide design rule reviews for IP, chip, and package designs for product release sign off

• Provide support for timing, physical verification signoff to make IP & ASIC designs robust

• Perform WAT & yield analysis on testchips and products to evaluate IP margins & robustness

• Work with IP design teams to support adaptation of existing IP into various semiconductor packaging environments

• Assist with technology road mapping activity for selection of appropriate semiconductor and packaging technology for ASICs to meet end customer requirements

Education & Experience

• Bachelor’s degree in electrical engineering and 8+ years (OR) Master’s degree and 6+ years (OR) PhD and 3+ years ofexperience in semiconductor process technology and manufacturing, specifically R&D and integration roles

Compensation and Benefits

The annual base salary range for this position is $107,000 - $190,000.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.