המקום בו המומחים והחברות הטובות ביותר נפגשים
Job duties include:
Architect and develop scalable and reusable Testbench environment using the framework of Verification Methodologies.
Drive Test plans for all features for Block/Core/SOC and Write Functional coverage for these features.
Build pseudo-random tests to verify and get to full Functional coverage and bring the Verification to closure
Debug Regression failures, analyze Functional Coverage gaps and improve tests to cover the gaps
Think differently and out-of-the-box to stress the DUT and verify it in an efficient way.
Lead the documentation of verification strategy including Test plans, Verification Environment, pseudo-random tests, etc. Lead reviews with design/architecture.
Driver Verification quality and Efficiency improvements
Mandatory Requirements:
Bachelor's degree in Electrical Engineering or related degree and 12+ years related experience or Master's degree in Electrical Engineering or related degree and 10+ years related experience
Decade+ experience in developing complex Verification Environments, developing Test plans, Functional coverage and pseudo-random testing
Must have gone through a full ASIC cycle right from Architecture development to Tapeout with full focus on Verification
Very proficient in System Verilog and Verification Methodologies like UVM/VMM
Good debug skills in analyzing regression failures and understanding of complex designs
A good understanding of a layered complex protocols like PCI Express or other multi-layered protocol
These requirements are a plus:
Scripting knowledge of Python or Perl
Comfort with Makefiles
Experience with Verifying with other protocols like AXI
Compensation and Benefits
The annual base salary range for this position is $126,000 - $210,000.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
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