המקום בו המומחים והחברות הטובות ביותר נפגשים
Job Description:
Job Description:
This opening is for working on chips that enable Physical Layer Products for High Speed Optical Communication.
architect block level design specifications from the marketing requirements and/or system requirements
prepare detailed design document, timing constraint file
RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA, RTL/gate level simulations & silicon debug
Scripting for various IC design tasks such as STA, equivalency checks, test bench, simulations, synthesis, etc.
prepare block level resource requirements & development schedule
generate verification & test plans for design validation
Perform design tradeoff analysis – leakage, dynamic power, die size, schedule, resource, priority, etc.
silicon bring up and validation, ATE program bring up
Job Requirement:
Good knowledge of ARM subsystem
Good knowledge of high speed digital circuit design.
Good knowledge of digitalupsampling/downsampling
Good knowledge of10G/100G/200G/400G/800GEthernet and OTN network.
Good knowledge on FEC (Forward Error Correction) design.
Good knowledge of digital signal processing and error correction code is a plus
Strong analytical and problem solving skills as well as hands-on lab debugging experiences
Good knowledge of RTL simulation and synthesis.
In-depth knowledge for design for low power and design for test and design for manufacturing.
Good Knowledge in languages relevant to the ASIC development process including Verilog, VHDL, Unix/Perl Scripting or Python, and C.
Self-motivated, excellent communication skills and ability to excel in a team environment.
Good organization skills, able to follow through & bring issue to closure
Understand the entire IC development flow & procedure including silicon volume production qualification requirements & procedures
Enthusiastic & enjoy IC development works
Be able to work with teams at remote locations with different time zone.
Compensation and Benefits
The annual base salary range for this position is$141,000 -$225,000
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
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