Microsoft Senior Silicon Engineer - IO 

United States, California 

143531379

Required/Minimun Qualifications:

• 7+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 5+ years of RTL design and/or architecture experience
• In depth domain knowledge of General purpose I/O protocols, including but not limited to GPIO, UART, I2C, and I3C
• In depth domain knowledge of Memory interface, including but not limited to NVDIMM, NOR Flash, and eMMC

Other Requirements:

Abilityto meet Microsoft, customer and/or government security screening requirementsrequired for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• Hands-on experience in integrating 3^rdparty IP, such as IO Pads and PLLs
• Understanding of Clock Domain Crossing design techniques
• Proficiency in Verilog, System Verilog, Synthesis and Static Timing Analysis

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:Microsoft will accept applications for the role until June 5, 2024.

As a Senior Silicon Engineer-IO in the Data Processing Unit team you will be validating silicon to solve complex problems in a datacenter. You will interact with the architecture team to develop a programmable silicon implementation. This position is expected to be highly visible and impactful. The vast breadth of domains required to build our DPU silicon gives the perfect opportunity to experience different areas of expertise. The depth required to solve complex engineering problems utilizes your experience and provides you with the perfect platform to shine and grow to the next stage in your career. Detail Responsibilities:

• Own the micro-architecture specification and RTL development of design modules for ASIC general purpose I/O block to facilitate system boot and chip management.
• Review and provide feedback on verification plans and methodology.
• Collaborate with Physical design teams to ensure design meets timing and area requirements.
• Work on post-silicon verification and debug.

• Embody our