Nvidia Senior Physical Design Methodology Engineer PPA Fusion Compiler 

United States, Texas 

118620430

What you will be doing:

• Developing Efficient physical design methodologies for implementation of graphics processors and SOCs.

• Key responsibility includes developing unique and creative solutions to the state-of-the-art physical design problems to improve PPA

• Participate in developing flow and tool methodologies for P&R, timing analysis and closure, convergence in IR/Signal-EM, power and noise analysis and back-end verification across multiple projects along with chip floorplan, power and clock distribution, chip assembly.

• Extensive timing knowledge to support timer for implementation to convergent implementation.

• Data based analysis and algorithmic solutions for PPA check and improvement.

What we need to see:

• MS in Electrical or Computer Engineering (or equivalent experience)

• Minimum 5 years’ experience in Physical Design Engineering

• Familiar with aspects of chip design including Floor planning, Clock and Power distribution, Place and Route, Integration and Verification.

• Staring knowledge of Physical design with convergence in timing/EM/IR with best PPA

• Strong background with hierarchical design approach, top-down design, budgeting, timing and physical convergence.

• Familiar with various process related design issues including Design for Yield and Manufacturability, EM and IR closure and thermal management.

• Solid understanding of industry standard PnR tools and analysis tools, Capable of extensive scripting to check and improve PPA