Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
5 years of experience with physical design flow such as constraints, synthesis, floor planning, place and route, clock tree synthesis (CTS), or physical verification.
Experience in one or more sign-off convergence areas.
Experience in high-speed design, including implementation and Power Performance Area, leveraging industry-standard tools.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
Experience in the delivery of high performance silicon in latest technology process nodes.
Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
Knowledge of Static Timing Analysis including sign-off corner definitions.
Knowledge of electromigration, voltage drop flows, and design for high frequency designs to support reliability.