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Intel GPU SoC Validation Engineer United States, California 100185537
Responsibilities includes but not limited to:
Defines, develops, and performs functional validation for GPUs, focusing on validation of interaction of GPUs, media, display and system level features.
Applies various hardware and software level tools and techniques to ensure validation coverage and that performance, power, and area goals are met.
Reviews proposed design changes to assess impact on validation plans, tasks, and timelines.
Develops GPU validation methodologies, executes validation plans, and collaborates with other engineers for design optimization, troubleshooting, and failure analysis.
Performs silicon debug to identify root causes and resolves all functional and triage failures for GPU issues.
Tests interactions between various GPU features using validation infrastructure.
Develops post silicon validation infrastructure (e.g., performance monitors, behavioral checkers, state space coverage) and test environment used in validation testing.
Publishes GPU validation reports summarizing all validation activities performed, reviews results, and communicates to relevant teams.
Works with architecture, design, verification, board, platform, and manufacturing teams to maintain and improve debug, validation test strategy, methodologies, and processes for graphics interfaces and to meet desired product specifications.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 1+ years of industry experience, or
Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 1+ years of industry experience, or
PhD in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 1+ years of industry experience.
Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous job and/or internship experience.
Possess an in-depth understanding of hardware architectures, system level IC design implementation, and knowledge of how to create end use scenarios
Prior work experience on IP level or Soc level
Good understanding of processor-based Soc level verification?which includes native Verilog, SystemVerilog and UVM mixed environments
Hands-on experience with verification tools such as VCS, waveform analyzer and? third-party VIP/BFM integration (eg. Synopsys VIPs)
Hands-on experience in UVM. C/C++, SystemVerilog verification language
Strong understanding of design concepts and ASIC flow
Preferred Qualifications and experience that will make you stand out:
Prior work on GDDR memory, power management, peripherals, datapath verification or PCIe Protocol is desirable
Good understanding of AXI-AMBA. Protocol variants is desirable
Strong technical background in FPGA prototype emulation, and debug
Proven technical background in silicon validation, failure analysis and debug
Good knowledge of validating system level designs based on embedded processors and peripherals such as SPI, I2C, UART
Prior hands-on automation script development and optimization (using C, Python)
Knowledge and experience in embedded firmware development
Good understanding of embedded firmware/software development process
Functional knowledge and experience in JTAG
*Salary range dependent on a number of factors including location and experience
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