דרושים Gpu Validation Engineer ב-אינטל ב-United States, California

Physical Design Implementation

• Execute complete physical design flow for custom CPU designs from RTL to GDS, creating manufacturing-ready design databases
• Perform synthesis, place and route, clock tree synthesis, floorplanning, and power/clock distribution for complex CPU cores
• Conduct static timing analysis, reliability analysis, and power/noise analysis for high-performance processor designs
• Optimize CPU designs to improve critical product parameters including power, frequency, and area

Verification & Signoff

• Execute comprehensive verification and signoff processes including formal equivalence verification and static timing analysis
• Perform reliability verification, static and dynamic power integrity analysis, and layout verification
• Conduct electrical rule checking (ERC) and structural design checking to ensure manufacturing compliance
• Ensure design quality and manufacturability across all verification domains

CPU-Specific Expertise & Optimization

• Apply specialized knowledge in CPU structural and physical design including physical clock design and timing closure
• Perform coverage analysis, multiple power domain analysis, structured placement, and routing optimization
• Implement design-for-test (DFT) methodologies specific to CPU architectures
• Collaborate closely with logic, circuit, architecture, and design automation teams to optimize microarchitectures

Technology Leadership & Innovation

• Work with industry EDA vendors to build and enhance tool capabilities for high-speed, low-power synthesizable CPU design
• Analyze design results and provide recommendations to improve current and future CPU microarchitectures
• Participate in development and improvement of physical design methodologies and flow automation
• Drive adoption of advanced design techniques and emerging technologies

Qualifications:

The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / orschoolwork/classes/research.The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or STEM-related field of study
• 2+ years of experience in VLSI circuit design and synthesis
• 1+ years of experience in static timing analysis
• 1+ years of experience in low power design methodologies
• Experience with physical design EDA tools (i.e. Synopsys, Cadence, Mentor Graphics)
• Experience with timing closure, power optimization, and signal integrity analysis

Preferred Qualifications

• Postgraduate degree (Master's/PhD) in Computer Engineering, Computer Science, Electrical Engineering, or STEM-related field of study
• Experience with x86 CPU architecture and Intel processor designs
• Experience with Tcl, Perl, Python Programming
• Experience in CPU microarchitecture and high-performance design principles

What We Offer

• Competitive compensation and comprehensive benefits
• Opportunity to work on industry-leading CPU architectures and technologies
• Access to cutting-edge EDA tools and advanced process technologies
• Collaboration with world-class CPU architects and design engineers
• Professional development and career advancement opportunities
• Direct impact on products powering global computing infrastructure

Experienced HireShift 1 (United States of America)US, California, Folsom
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 104,890.00 USD - 197,230.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Job Description:

Since pioneering the world’s first hybrid silicon laser, IPS has led the industry in scalable, high-volumemanufacturing andadvanced photonics development. Our mission: deliver next-generation bandwidth growth with smaller form factors, co-packaging, and speeds from 400G today to 1.6T+ tomorrow.

We are seeking a Lead Analog SerDes Architect / Design Engineer to join our team and shape the future of data center connectivity. In this role, you will:

• Defining circuit architecture and enabling designs meeting power, and performance for next generation optical interconnects based on system specifications.
• As part of the team developing key integrated circuit components the engineer must be able to work collaboratively leading block level development.
• Specify, architect and design low voltage and low power Mixed-Signal integrated circuits and work collaboratively with digital designers.
• Plan design work with constraints on performance, schedule and quality.
• Provide guidance to junior designers and layout engineers.
• Guidance to develop test plans for post-silicon characterization.
• Document all design work with review materials and detailed design descriptions.

Minimum QualificationsThe ideal candidate should have a minimum of MS in Electrical Engineering with 8+ years of experience in high-speed serial links and deep knowledge of analog CMOS/BiCMOS designs in deep sub-micron process technologies.• Hands-on circuit design experience of SerDes blocks like Equalizers, PLL, Phase-Interpolators, CDR, etc. for 28Gbps+ data rates.
• Experience with design of inductors, transmission line, Trans-Impedance Amplifiers (TIA) and modulator drivers.
• Experience with design of precision analog circuits like ADC/DACs.
• Experience with designing PAM4/NRZ links.
• Experience with Mixed signal design flow
• Experience with full-chip designs, ESDs and verification flows.
Preferred Qualifications
• Familiarity with Optical communications.
• Experience with 400G/800G/1.6T optical links.
• Experience with package/test setup design.

Experienced HireShift 1 (United States of America)US, California, Santa Clara
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 214,730.00 USD - 303,140.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

WHO YOU ARE

Responsibilities include, but are not limited to:

• Performs functional logic verification of an integrated SoC to ensure design will meet specifications.

• Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.

• Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.

• Replicates, root causes, and debugs issues in the presilicon environment.

• Finds and implements corrective measures to resolve failing tests.

• Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.

• Documents test plans and drive technical reviews of plans and proofs with design and architecture teams.

• Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.

• Maintains and improves existing functional verification infrastructure and methodology.

• Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages and proliferates to future products.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 1+ years of relevant experience

— or —

Master’s degree in the same fields

Relevant work experience should be of the following:

• Experience with UVM
• Experience with System Verilog
• Experience with Design Verification
• Experience with Computer Architecture
• Experience with Hardware Verification

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

College GradShift 1 (United States of America)Virtual US
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 90,890.00 USD - 170,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 11/25/2026

Job Description:

Responsibilities include, but are not limited to:

• Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design.

• Participates in the definition of architecture and microarchitecture features of the block being designed.

• Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence.

• Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.

• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

• Follows secure development practices to address the security threat model and security objects within the design.

• Works with IP providers to integrate and validate IPs at the SoC level. Drives quality assurance compliance for smooth IPSoC handoff.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

This is an entry level position and will be compensated accordingly.

Minimum qualifications:

Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 1+ years' experience withScripting (python, pearl, or other similar programming languages)

— or —

Master’s degree or PhD in the same fields

Preferred qualifications:

• UPF coding.

• Integrating and ensuring IP components within SOC

• Implementing physical connectivity

• Testing and verification

Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research and relevant previous job and/or internship experience.

College GradShift 1 (United States of America)Virtual US
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 90,890.00 USD - 170,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 08/31/2026

Physical Design Implementation

• Execute complete physical design flow for custom CPU designs from RTL to GDS, creating manufacturing-ready design databases
• Perform synthesis, place and route, clock tree synthesis, floorplanning, and power/clock distribution for complex

CPU Cores

• Conduct static timing analysis, reliability analysis, and power/noise analysis for high-performance processor designs
• Optimize CPU designs to improve critical product parameters including power, frequency, and area

Verification & Signoff

• Execute comprehensive verification and signoff processes including formal equivalence verification and static timing analysis
• Perform reliability verification, static and dynamic power integrity analysis, and layout verification
• Conduct electrical rule checking (ERC) and structural design checking to ensure manufacturing compliance
• Ensure design quality and manufacturability across all verification domains

CPU-Specific Expertise & Optimization

• Apply specialized knowledge in CPU structural and physical design including physical clock design and timing closure
• Perform coverage analysis, multiple power domain analysis, structured placement, and routing optimization
• Implement design-for-test (DFT) methodologies specific to CPU architectures
• Collaborate closely with logic, circuit, architecture, and design automation teams to optimize microarchitectures

Technology Leadership & Innovation

• Work with industry EDA vendors to build and enhance tool capabilities for high-speed, low-power synthesizable CPU design
• Analyze design results and provide recommendations to improve current and future CPU microarchitectures
• Participate in development and improvement of physical design methodologies and flow automation
• Drive adoption of advanced design techniques and emerging technologies

Qualifications:

The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / orschoolwork/classes/research.The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or STEM-related field of study
• 5+ years of experience in VLSI circuit design and synthesis
• 4+ years of experience in static timing analysis
• 4+ years of experience in low power design methodologies
• Experience with physical design EDA tools (i.e. Synopsys, Cadence, Mentor Graphics)
• Experience with timing closure, power optimization, and signal integrity analysis

Preferred Qualifications

• Postgraduate degree (Master's/PhD) in Computer Engineering, Computer Science, Electrical Engineering, or STEM-related field of study
• Experience with x86 CPU architecture and Intel processor designs
• Experience with Tcl, Perl, Python Programming
• Experience in CPU microarchitecture and high-performance design principles

What We Offer

• Competitive compensation and comprehensive benefits
• Opportunity to work on industry-leading CPU architectures and technologies
• Access to cutting-edge EDA tools and advanced process technologies
• Collaboration with world-class CPU architects and design engineers
• Professional development and career advancement opportunities
• Direct impact on products powering global computing infrastructure

Experienced HireShift 1 (United States of America)US, California, Folsom
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 139,710.00 USD - 262,680.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

WHO YOU ARE:

As an IP Logic Design Engineer your responsibilities will include but are not limited to:

• Designing and/or integrating IP for Intel's Custom Silicon solutions.

• You will be working or assisting in architecture, design, implementation, formal verification, emulation and validation.

• Creating a design to produce key assets that help improve product KPIs for discrete graphics products.

• Working with SoC Architecture and platform architecture teams to establish silicon requirements.

• Making appropriate design trade off balancing risk, area, power, performance, validation complexity and schedule.

• Creating micro architectural specification document for the design.

• Working with external vendors on tools or IPs required for the development of micro-architecture, design and design qualification of custom silicon designs.

• Driving vendor's methodology to meet world class silicon design standards.

• Architecting area and power efficient low latency designs with scalabilities and flexibilities.

• Power and Area efficient RTL logic design and DV support.

• Running tools to ensure lint-free and CDC/RDC clean design, VCLP.

• Synthesis and timing constraints.

• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 3+ years of relevant experience

— or —

Master’s degree in the same fields with 2+ years of relevant experience

— or —

PhD in the same fields.

Relevant work experience should be of the following:

• xperience with complex IP/ASIC/SOC Design Implementation.

• Experience in system and processor architecture.

• Experience with System Verilog/SOC development environment.

Preferred Qualifications:

• Experience in scripting languages (i.e. PERL, TCL, or Python).

• Experience with Hardware validation techniques (i.e. formal Verification, Test and Function Verification).

• Experience designing and implementing complex blocks like CPUs, GPU, Media blocks, and Memory controller.

• Experience in leading small team of engineers.

• Experience with Industry standard protocols (i.e. PCIE, USB, DDR, etc).

• Experience with interaction of computer hardware with software.

• Experience with Low power/UPFimplementation/verificationtechniques.

• Experience with Formal verification techniques.

Experienced HireShift 1 (United States of America)Virtual US
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 121,050.00 USD - 227,620.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 08/31/2026

What Intel offers:

• We give you opportunities to transform technology and create a better future, by delivering products that touch the lives of every person on earth.
• As a global leader in innovation and new technology, we foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results.
• We offer a competitive salary and financial benefits such as bonuses, life and disability insurance, opportunities to buy Intel stock at a discounted rate, and Intel stock awards (eligibility at the discretion of Intel Corporation).

As a Software Application Development Engineer, you will:

Design, develop, test, and debug software applications used by end users or integrated with other applications by ISVs (Independent Software Vendors). Development may span the full application stack, including frontend and backend application development.

Use modern software development methodologies and programming languages.

Follows secure coding practices and software legal compliance guidelines.

Analyze user stories, write functional and test code, automate build and deployment, and perform unit integration and end-to-end testing of applications.

Complete SDL tasks with the assistance of product security engineers and provide input to technical writers to complete product documentation and procedures for installation and maintenance.

May also interact with end users to define system requirements and/or necessary modifications.

Applicants should possess the behavioral traits below:

Demonstrated data analytics skills to communicate complex data in a simple, actionable way.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are a plus factor in identifying top candidates.Experience listed below would be obtained through a combination of yourschoolwork/classes/researchand/or relevant previous job and/or internship experiences.

What we need to see (Minimum Qualifications):

• US Citizenship Required.
• Ability to obtain and maintain active US Government Security Clearance.
• Bachelor's degree in computer science, computer engineering, electrical engineering, or a similar field and 6+ years' is relevant experience OR a master’s degree in computer science, computer engineering, electrical engineering, or a similar field and 3+ years' relevant experience.
• Proven Engineering Excellence: 4+ years of professional software development experience with deep expertise in both dynamically-typed languages (Python, JavaScript, etc.) and statically-typed languages (Java, C++, etc.), with a track record of delivering high-impact solutions
• Advanced Technical Mastery: Expert-level (4+ years’ experience) with data structures and algorithms, with the ability to architect optimal solutions using complex data structures (trees, graphs, hash maps ) and make informed trade-offs between performance, memory usage, and maintainability.
• Design Leadership: (4+ years'experience). withsoftware design patterns and architectural principles, with proven ability to design scalable systems, lead technical decision-making, and establish coding standards that solve complex business challenges at scale
• Collaborative Technical Excellence: 2+ years’ experience sharing knowledge and best practices with team members through code reviews, pair programming, and technical discussions. You enjoy helping colleagues grow while maintaining focus on your own technical deliverables and project contributions.

Preferred Qualifications:

• Master degree in computer science or a related field and 8+ years' experience.
• Semiconductor Fabrication and Lithography.
• Knowledge of EDA (Electronic Design Automation) tools.
• Database Concepts, SQL and hardware platform architecture, networking.
• Distributed computing and/or multi-threading experience.
• Information Security protocols.
• Experience with full-stack web development.

Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.

Experienced HireShift 1 (United States of America)US, California, Santa Clara
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 132,810.00 USD - 258,410.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.