דרושים Micro-architect/logic Designer Memory Controller ב-Samsung ב-United States, Austin

Role and Responsibilities

• Manage projects related to incoming technology transfer, new product introductions, yield improvement, stop loss reduction, cycle time reductions and other KPI improvements.

• Design, execute, and analyze experiments.

• Uses software to analyze data including statistical analysis; Consults with leadership team on experimental results in order to make decisions about large-scale changes.

• Responsible for critical or complex steps or layers in the wafer fabrication process.

• Trouble shooting issues affecting Yield, defect, electrical performance of products

• Develops Change Point Management Plans.

• Communicates technical information with presentation.

Education, Training, Certification(s) and Minimum # Years Required:

• Bachelor’s degree in Physics, Chemistry, Electrical Engineering, Chemical Engineering, Materials Science or related field is required.

• Master's or Ph.D. is preferred.

• Basic understanding of some unit processes including thin films deposition, lithography, etch, diffusion, wet process, Cu plating, and CMP.

• Basic understanding of the interactions between process and yield.

• Electrical Engineering, Materials Sciences, and Physics expertise within semiconductor field is required.

• Must have basic understanding of Semiconductor process flow in assigned areas.

• Experience in Yield or Process Integration in semiconductor manufacturing is strongly preferred.

• Experience with Foundry Customer communication is strongly preferred.

• Experience with development is strongly preferred.

• Experience with DDI Process Integration is preferred.

Note: This position is Full-Time onsite.

We offer a comprehensive benefits package, including:

• Medical, dental, and vision insurance
• Life insurance and 401(k) matching with immediate vesting
• Onsite café(s) and workout facilities
• Paid maternity and paternity leave
• Paid time off (PTO) + 2 personal holidays and 10 regular holidays
• Wellness incentives and MORE
  

All positions at SAS are full-time on-site.

This role requires access to information subject to U.S. export control laws. Applicants must be authorized to access such information or eligible for government authorization.

Role and Responsibilities

As a Lead Memory Controller Architect/uArch, you will drive the design and development of advanced memory controller for cutting-edge technologies such as LPDDR5, LPDDR6, PIM (Processing in Memory), and beyond (DDR5, GDDR7, HBM4).

As a key player in this critical position, you will have end-to-end ownership for memory-controller architecture, including microarchitecture, RTL design, and performance/power optimization. You will work closely with cross-functional teams, such as system architects, verification, performance/power, and design implementation, to bring innovative ideas to life and develop cutting-edge memory technologies for Samsung's next-generation products. This role offers a unique opportunity to be at the forefront of the entire technology development cycle, allowing you to expand your expertise in memory controllers and push the boundaries of what is possible, shaping the future of memory technology.

• You possess a strong engineering foundation and extensive experience in architecture, enabling you to lead the development of custom memory controllers, including micro-architecture, RTL design, debugging, and timing closure.
• You have a passion for microarchitecture development, excel at driving the creation of high-quality RTL from initial architectural exploration to final delivery, meeting performance, power, and area (PPA) targets while adhering to project schedules.
• You ensure design excellence, utilizing various tools and methodologies, including LINT, CDC, ECO flows, and power analysis (PowerArtist), to validate design quality and identify areas for improvement.
• You collaborate with cross-functional teams, you foster strong partnerships with stakeholders to guarantee design functionality, achieve PPA objectives, and overcome implementation challenges in a dynamic environment with shifting priorities.
• You take pride in your deliverables, assuming ownership of your work by adhering to JEDEC standards, collaborating with SOC IP delivery teams, performing thorough sanity checks, supporting timing debug and closure, and applying your knowledge of DDR PHY to drive successful outcomes.

Skills and Qualifications

• 20+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 18+ years of experience with a Master’s Degree, or 16+ years of experience with a PhD
• Proven experience in memory controller micro-architecture and RTL design, owning all sub-blocks of custom memory controller designs.
• Deep expertise in multiple memory technologies, such as LPDDR4/5/6, PIM, DDR, GDDR, and HBM.
• Strong knowledge of JEDEC memory standards and working knowledge of DDR PHY.
• Demonstrated success in driving architecture through RTL design for high-performance digital systems.
• Strong expertise in Verilog and ASIC design flow, including RTL design, verification, synthesis, timing analysis, and ECO.
• Proficiency in scripting languages (Perl, Python) to support design and automation.
• Strong communication and collaboration skills; able to navigate ambiguity in a fast-paced, global team environment.
• Familiarity with interface protocols (AMBA, AXI, ACE) is desired.
• Knowledge of AES, ECC, and RAS features is preferred.
• Self-driven, curious, and passionate about logic design and innovation.

With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture.

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.

Role and Responsibilities

As a Sr. Memory Controller Micro-Architect, you will lead the design and development of advanced memory controller for cutting-edge technologies such as LPDDR5, LPDDR6, PIM (Processing in Memory), and beyond (DDR5, GDDR7, HBM4).

In this high-impact role, you will have ownership and influence entire memory-controller related micro-architecture, RTL design, and performance/power optimization.As part of a true global task force, you will collaborate closely with system architects, verification, performance/power, design implementation, and other teams to transform bold ideas into next-generation memory technologies for Samsung. You are empowered to deepen your expertise in memory controller by being at the forefront of a full technology development cycle and redefining what’s possible.

• You are a domain expert in one or more technical areas with solid engineer foundation and RTL design experience. You will drive the micro-architecture, RTL design, debug, and timing closure for custom memory controllers.
• You are passionate about handling microarchitecture development and specification – from early high-level architectural exploration through micro architectural research and delivering high quality RTL on schedule to meet performance, power, an area (PPA) goals.
• You ensure design quality through LINT, CDC, ECO flows, and power analysis (PowerArtist).
• You have a collaborative mindset and build strong cross-functional partnerships with various stakeholders to ensure design functionality, achieve PPA goals, and resolve implementation challenges with evolving priorities in a fast-paced environment.
• You take ownership in your deliverables by adhering to JEDEC standards and timing parameters, collaborating with SOC IP delivery with all sanity checks, supporting timing debug and closure, and applying knowledge of DDR PHY.

Skills and Qualifications

• 20+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 18+ years of experience with a Master’s Degree, or 16+ years of experience with a PhD
• Proven experience in memory controller micro-architecture and RTL design, owning all sub-blocks of custom memory controller designs.
• Deep expertise in multiple memory technologies, such as LPDDR4/5/6, PIM, DDR, GDDR, and HBM.
• Strong knowledge of JEDEC memory standards and working knowledge of DDR PHY.
• Demonstrated success in driving architecture through RTL design for high-performance digital systems.
• Strong expertise in Verilog and ASIC design flow, including RTL design, verification, synthesis, timing analysis, and ECO.
• Proficiency in scripting languages (Perl, Python) to support design and automation.
• Strong communication and collaboration skills; able to navigate ambiguity in a fast-paced, global team environment.
• Familiarity with interface protocols (AMBA, AXI, ACE) is desired.
• Knowledge of AES, ECC, and RAS features is preferred.
• Self-driven, curious, and passionate about logic design and innovation.

With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture.

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.

Role and Responsibilities

As a GPU Performance Architect (Memory System), you will work as part of the GPU Architecture team where you will drive the modeling and analysis of memory-system features for a highly efficient mobile GPU. You have a curious mindset that thrives on navigating the unknown through innovation and continuous learning. You will contribute towards current and future plans strategy.

We believe in connecting your area of expertise with the right level and functional discipline that can empower you to grow. You will have the unique opportunity to explore and contribute to the graphics pipeline, while broadening your knowledge in different aspects of GPU development.

• You work closely with the architecture, SW, and design teams to understand the architecture and micro-architecture of the GPU memory system including cache hierarchy, bus unit, interfaces with the GPU core and rest of the SoC.
• You develop complex GPU performance models to help define micro-architectural features and implementation optimizations of next-generation GPUs, in areas of memory system.
• You develop tools and methodology to correlate and validate performance models, triage and fix performance issues, and identify bottlenecks and propose solutions to improve GPU performance.
• You drive high-level performance analysis on complex workloads, with the goal to optimize the GPU with rest of the Memory System IP (Interconnect, Last-level Cache, Memory Controller).

Skills and Qualifications

• 10+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 8+ years of experience with a Master’s Degree, or 6+ years of experience with a PhD
• 5+ years of experience in architectural modeling and performance analysis, either with analytical models or cycle-accurate simulators
• Experience with CPU, GPU, or Memory systems microarchitecture
• Good programming and/or scripting skills (Python is a plus)
• Good understanding of power/performance trade-offs
• Good understanding of VLSI concepts, HW design
• Good written and verbal communication skills

• Performance modeling or workload analysis experience, in areas of memory subsystems
• Knowledge of Core Pipelines (CPU, GPU or Accelerators)
• Directly related experience with correlation of RTL with performance model
• Experience in integrating internal/external IP models on a full system-level framework.

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.

Role and Responsibilities

As a Sr. Memory ControllerMicro-Architect/LogicDesigner, you will contribute to the micro-architecture development and logic design of our advanced custom memory controller for LPDDR5/6. This is a senior level role where you will interact with the system architects, verification, performance/power and design implementation teams. You will be own and drive the critical memory controller related RTL design, performance and power optimization, and also work on logic debug and timing closure of the design. Solid engineer foundation and RTL design experience are desired for success.

• You drive the timely development and debug of new features on timely development of custom memory controller.
• You work on SOC IP delivery with all sanity checks.
• You work on timing debug and closure.
• You work on LINT, CDC flows and analysis.
• You work on power artist flow and power analysis.
• You have experience working on ECO flows.
• You collaborate with the verification team to verify the functionality and correctness of the design.
• You communicate with implementation to achieve your timing and area.
• You produce high quality RTL on schedule meeting PPA goals
• You engage with performance and power team on achieving performance and power goals.
• You partner with the physical design and CAD team to resolve implementation level details.

Skills and Qualifications

• 15+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 13+ years of experience with a Master’s Degree, or 11+ years of experience with a PhD
• Strong background owning and driving the RTL design of various sub-blocks of custom memory controller designs
• Experience working with memory controller u-architecture on different memory technologies like LPDDR5/6, GDDR, PIM, HBM
• Demonstrated experience of successful Architectural through RTL design on high performance digital designs
• Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis & ECO
• Knowledge of JEDEC memory standards preferred
• Understanding of interface protocols such as AMBA, AXI, ACE is desired
• Knowledge of AES, ECC, RAS features preferred
• Strong communication and interpersonal skills are required, along with the ability to work in a dynamic, global team
• Experience with a scripting language like Perl or Python
• Energetic, curiosity, and passion in logic design

With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture.

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.

Role and Responsibilities

As a Senior Coherent Interconnect Micro-Architect, you will be responsible for leading the micro-architecture development of custom coherent interconnect IP and/or last level cache blocks. In this role you will be interacting with the system architects, verification, performance/power and design implementation teams. You will be owning and driving the critical coherent interconnect related RTL design, performance and power optimization and also work on logic debug and timing closure of the design. Solid engineer foundation and RTL design experience are desired for success.

• You drive the timely development of custom coherent interconnect IP and/or last level cache [LLC] blocks.
• You engage with the architects and help define next-generation Samsung coherent interconnects and LLC.
• You perform microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specification
• You work with the verification team to verify the functionality and correctness of the design.
• You collaborate with implementation to achieve your timing and area.
• You produce quality RTL on schedule meeting PPA goals
• You engage with performance and power team on achieving performance and power goals.
• You partner with the physical design and CAD team to resolve implementation level details.
• You Help mentor junior engineers in the team.

Skills and Qualifications

• 15+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 13+ years of experience with a Master’s degree, or 11+ years of experience with a PhD
• Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for the high performance digital designs
• Demonstrated experience of successful Architectural through RTL design experience on high performance digital designs
• Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
• Knowledge of system caches and directory snoop filter protocols.
• Familiarity with different on-chip network topologies: mesh, ring, crossbar.
• Experience in leading and mentoring a team of engineers.
• Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols
• Knowledge of memory subsystem design including coherent cache design.
• Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.

• Knowledge of Verilog/VHDL, scripting, STA, DFT, ECO flows.
• Proficient in AMBA, ACE, AXI, CHI protocols.
• Knowledge of memory controller and either coherent interconnect or cache design.
• Knowledge of memory subsystem, coherency, directory snoop filter protocols.
• Familiarity with different on-chip network topologies: mesh, ring, crossbar.
• Experience with a scripting language like Perl or Python.
• Energetic, curiosity, and passion in logic design.
• Good written and verbal communication skills.
• Efficient digital design techniques.

With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture.

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.

Role and Responsibilities

As a Senior Performance Architect within our System IP team, you will play a critical role in designing and optimizing the performance of our System IP, balancing requirements from key system components including CPU, GPU, and other IP blocks. You will be responsible for developing and maintaining performance models, analyzing system performance, and identifying optimization opportunities to improve overall system efficiency. Your expertise in performance modeling, analysis, and C++ coding will be essential in driving the development of high-performance System IP solutions. Specialized experience working on memory subsystem, including interconnect, last-level cache, coherency, and memory controller is a big plus.

• You develop and maintain cycle-accurate C++ performance models for System IP components.
• You analyze system performance using various metrics, such as latency, throughput, and power consumption, to identify bottlenecks and optimization opportunities.
• You develop and maintain performance analysis tools.
• You collaborate with cross-functional teams, including architecture, design, and software teams, to identify and implement performance optimization opportunities.
• You develop and run benchmarks to characterize system performance and identify areas for improvement.
• You provide technical guidance and mentorship to junior engineers and contribute to the development of best practices and standards for performance modeling and analysis.
• You work closely with other teams, including CPU, GPU, and SoC architecture teams, to ensure that System IP components meet performance and power requirements.

Skills and Qualifications

• 15+ years of professional experience with a Master’s Degree in Computer Science, Engineering, or related field.
• Expertise in performance modeling, analysis, and optimization, with a focus on System IP components.
• Strong C++ coding skills, with experience developing cycle-accurate performance models and analysis tools.
• Strong understanding of computer architecture, microarchitecture, and system-level performance optimization.
• Excellent analytical and problem-solving skills, with the ability to identify and optimize performance bottlenecks.
• Strong technical leadership and mentoring skills, with experience guiding junior engineers.

• Professional experience in memory subsystem or interconnect, with knowledge of memory hierarchy, memory access patterns, bandwidth, and latency optimization, is a big plus.
• A Ph.D. in a related field, with a focus on performance modeling and analysis.
• Proficiency in performance modeling tools such as SystemC, Gem5, or similar.
• Experience with industry standard RTL design tools and methodologies.
• Programming skills in Python or R, with experience in data analysis, visualization, and automation.
• Familiarity with emerging technologies, such as AI, ML, and autonomous systems, and their impact on System IP performance.

With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture.

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.