Samsung Sr Performance Architect 

United States, Texas, Austin 

31190078

Role and Responsibilities

As a Senior Performance Architect within our System IP team, you will play a critical role in designing and optimizing the performance of our System IP, balancing requirements from key system components including CPU, GPU, and other IP blocks. You will be responsible for developing and maintaining performance models, analyzing system performance, and identifying optimization opportunities to improve overall system efficiency. Your expertise in performance modeling, analysis, and C++ coding will be essential in driving the development of high-performance System IP solutions. Specialized experience working on memory subsystem, including interconnect, last-level cache, coherency, and memory controller is a big plus.

• You develop and maintain cycle-accurate C++ performance models for System IP components.
• You analyze system performance using various metrics, such as latency, throughput, and power consumption, to identify bottlenecks and optimization opportunities.
• You develop and maintain performance analysis tools.
• You collaborate with cross-functional teams, including architecture, design, and software teams, to identify and implement performance optimization opportunities.
• You develop and run benchmarks to characterize system performance and identify areas for improvement.
• You provide technical guidance and mentorship to junior engineers and contribute to the development of best practices and standards for performance modeling and analysis.
• You work closely with other teams, including CPU, GPU, and SoC architecture teams, to ensure that System IP components meet performance and power requirements.

Skills and Qualifications

• 15+ years of professional experience with a Master’s Degree in Computer Science, Engineering, or related field.
• Expertise in performance modeling, analysis, and optimization, with a focus on System IP components.
• Strong C++ coding skills, with experience developing cycle-accurate performance models and analysis tools.
• Strong understanding of computer architecture, microarchitecture, and system-level performance optimization.
• Excellent analytical and problem-solving skills, with the ability to identify and optimize performance bottlenecks.
• Strong technical leadership and mentoring skills, with experience guiding junior engineers.

• Professional experience in memory subsystem or interconnect, with knowledge of memory hierarchy, memory access patterns, bandwidth, and latency optimization, is a big plus.
• A Ph.D. in a related field, with a focus on performance modeling and analysis.
• Proficiency in performance modeling tools such as SystemC, Gem5, or similar.
• Experience with industry standard RTL design tools and methodologies.
• Programming skills in Python or R, with experience in data analysis, visualization, and automation.
• Familiarity with emerging technologies, such as AI, ML, and autonomous systems, and their impact on System IP performance.

With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture.

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.