Samsung Sr Coherent Interconnect Micro-architect/Logic Designer 

United States, Texas, Austin 

724042105

Role and Responsibilities

As a Senior Coherent Interconnect Micro-Architect, you will be responsible for leading the micro-architecture development of custom coherent interconnect IP and/or last level cache blocks. In this role you will be interacting with the system architects, verification, performance/power and design implementation teams. You will be owning and driving the critical coherent interconnect related RTL design, performance and power optimization and also work on logic debug and timing closure of the design. Solid engineer foundation and RTL design experience are desired for success.

• You drive the timely development of custom coherent interconnect IP and/or last level cache [LLC] blocks.
• You engage with the architects and help define next-generation Samsung coherent interconnects and LLC.
• You perform microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specification
• You work with the verification team to verify the functionality and correctness of the design.
• You collaborate with implementation to achieve your timing and area.
• You produce quality RTL on schedule meeting PPA goals
• You engage with performance and power team on achieving performance and power goals.
• You partner with the physical design and CAD team to resolve implementation level details.
• You Help mentor junior engineers in the team.

Skills and Qualifications

• 15+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 13+ years of experience with a Master’s degree, or 11+ years of experience with a PhD
• Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for the high performance digital designs
• Demonstrated experience of successful Architectural through RTL design experience on high performance digital designs
• Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
• Knowledge of system caches and directory snoop filter protocols.
• Familiarity with different on-chip network topologies: mesh, ring, crossbar.
• Experience in leading and mentoring a team of engineers.
• Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols
• Knowledge of memory subsystem design including coherent cache design.
• Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.

• Knowledge of Verilog/VHDL, scripting, STA, DFT, ECO flows.
• Proficient in AMBA, ACE, AXI, CHI protocols.
• Knowledge of memory controller and either coherent interconnect or cache design.
• Knowledge of memory subsystem, coherency, directory snoop filter protocols.
• Familiarity with different on-chip network topologies: mesh, ring, crossbar.
• Experience with a scripting language like Perl or Python.
• Energetic, curiosity, and passion in logic design.
• Good written and verbal communication skills.
• Efficient digital design techniques.

With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture.

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.