דרושים Chip Power Architecture Lead ב-אנבידיה ב-ארהב

What you’ll be doing:

• Pre-silicon Power Estimation: Model and estimate CPU power at C-model, RTL, and netlist stages using industry-standard tools.

• Power Optimization: Identify inefficiencies and drive design improvements in collaboration with architects, RTL designers, and PD engineers.

• Test Development: Create targeted power characterization tests (e.g., peak power, di/dt stress patterns) for both simulation and silicon.

• Silicon Validation: Measure CPU power and performance in the lab; correlate silicon results with pre-silicon estimates to refine models.

• Cross-functional Collaboration: Partner with multiple engineering disciplines to achieve optimal power efficiency without compromising performance.

What we need to see:

• BS/MS in EE, CE, or CS or equivalent experience.

• 3+ years of experience working in ASIC power measurement and optimization.

• Strong understanding of leakage and dynamic power in VLSI circuits

• Experience with RTL and netlist power analysis tools such as Power Artist, PrimeTime PX, or equivalent.

• Familiarity with CPU microarchitecture (CPU pipeline design, out-of-order execution, cache hierarchy, branch prediction) and understanding of microarchitectural power model.

Ways to stand out from the crowd:

• Proficiency in Python for automation and data analysis.

• Experience with DVFS, clock gating, power gating, and multi-voltage domain design.

• Knowledge of lab instrumentation for power measurement.

• Strong communication skills for cross-team technical discussions.

What you'll be doing:

• Serve as the primary, high-impact contributor on complex features. Dedicate significant time to producing production code across the full stack, including UI, APIs, services, and infrastructure.

• Code Review Leadership & Quality Assurance: Lead the code review process, setting and implementing thorough coding standards, performance benchmarks, and architectural integrity to ensure all merged code is high-quality, maintainable, and robust.

• Architectural Ownership & Portability: Define and own the long-term technical roadmap, architecture, and design. This includes the required assurance that the deployment pipelines and services are platform-agnostic and easily deployable across the broader NVIDIA ecosystem, deliberately avoiding internal infrastructure dependencies.

• Foundation Model Deployment Strategy: Lead the strategic implementation of web services and efficient batch processing queues to seamlessly integrate and operationalize our world foundation models into the customer-facing platform.

• System Performance & Reliability: Implement and make sure standards for production-grade performance, monitoring, and fault tolerance across all services. Proactively identify and resolve systemic technical debt and scalability bottlenecks.

• Deployment & Operational Excellence: Take ultimate ownership of the CI/CD pipelines, container orchestration strategy (Kubernetes/Helm), and operational readiness, ensuring seamless scalability and reliability in production.

• Team Mentorship & Guidance: Mentor and guide the engineering team on advanced practices in full-stack development, distributed systems design, performance optimization, and clean, portable code architecture.

• Multi-functional Partnership: Act as the key technical liaison, translating complex requirements from Product Managers, ML Engineers, and Data Scientists into robust, portable, and implementable designs.

What we need to see:

This role requires a proven track record of significant experience and technical mastery:

• Minimum 12+ years of hands-on experience developing and deploying scalable full-stack web services in a cloud environment.

• Proven Tech Lead or equivalent Senior/Staff level experience with demonstrated ability to define system architecture, mentor engineers, and take end-to-end technical ownership of a major platform while remaining deeply active in coding and code reviews.

• Expert-level proficiency in designing and scaling distributed microservices architectures using gRPC and REST APIs.

• Deep expertise in modern frontend frameworks and building highly responsive, data-intensive UIs capable of managing high-frequency data flows.

• Direct experience designing and deploying containerized applications that use a GPU (e.g., NVIDIA Container Toolkit).

• Experience with MaaS (Model-as-a-Service) patterns and serving large machine learning models as high-throughput endpoints.

• Mastery of container orchestration, including Kubernetes and Helm for sophisticated, portable, multi-service production deployments.

• Proficiency in backend languages such as Python and/or Go, and TypeScript for the frontend.

• Strong practical experience with Cloud Infrastructure (AWS S3) and running complex data storage/access patterns (SQL, key-value stores).

• Expertise in CI/CD practices (GitLab, Jenkins) with a focus on automation, testing, and improving deployment velocity and stability.

• Bachelor's degree (B.S.) or equivalent experience in Computer Science, Software Engineering, Electrical Engineering, or a closely related technical field; Master's degree (M.S.) preferred

Ways to stand out from the crowd:

These skills represent a strong alignment with our specific domain challenges:

• Experience in data querying platforms such as Apache Druid, ClickHouse, or Elasticsearch.

• Familiarity with autonomous vehicle simulation environments (e.g., Carla) and synthetic data generation pipelines using foundational models.

Today, NVIDIA is tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. Come join the team and see how we can make a lasting impact on the world!

We are now looking for an Low Power Design/Verification ASIC Engineer - New College Grad 2026. We continue to rapidly grow the research and development of energy-efficient GPU and SOC architectures. We are continually innovating in creative and unrivaled ways to improve our ability to deliver exceptional perf/watt solutions in a wide range of sectors. Come join NVIDIAs Low Power DV team to develop state of the art GPUs to power AI, Automotive, GeForce, and Mobile products.

What you'll be doing:

• Working very closely with Low Power Architecture, Design, and Software teams to understand next generation features.

• Responsible forarchitecting/developingtestbench, infrastructure, and testplans to verify various power management solutions for NVIDIA products.

• You will have the opportunity bring creative ideas that help improve power-aware DV methodologies, as well as influence EDA vendors to improve our simulation and debug efficiencies.

What we need to see:

• Pursuing or recently completed a BS, MS or PhD in Electrical or Computer Engineering,or equivalent experience.

• You have an understanding of low power design techniques such as multi VT, Clock gating, Power gating, Block Activity Power, and Dynamic Voltage-Frequency Scaling (DVFS) etc.

• Good understanding of processor architecture (GPU is a plus), and related power management design/DV techniques.

• Must be experienced with Incisive Low-Power or Synopsys VCS NLP

• Strong debug skills and experience with Verdi is needed

• Must be fluent in Verilog, SystemVerilog, and understanding of UVM.

Ways to stand out from the crowd:

• Prior knowledge of Low Power Architecture, Low Power CV, and deep learning

• Good understanding of power intent in UPF format is a plus

• A strong background in Low Power architectures or verification is a plus.

• Scripting abilities in Python or PERL is a plus and knowledge of C or C++ is a plus

• Experience writing or maintaining the script or Makefile that builds the simulation program is a plus

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love a challenge? If so, we want to hear from you.

What you'll be doing:

• Analyzing and optimizing Silicon power and performance across technical, product, and usage constraints for Nvidia SoCs used in data center, driving, robotics, multimedia, edge computing, and other embedded applications.

• Working with teams throughout the company (HW, SW, Platform, Thermal, Operations, Marketing, etc...) to deliver outstanding power solutions.

• Guiding HW, SW and Platform teams in evaluating and improving Perf/Watt and battery life of their implementations.

• Creating power models of key SoC units to evaluate architectural tradeoffs in DL/ML(training/inference),CPU, GPU, and multimedia workloads.

What we need to see:

• A Master’s degree in Computer Engineering or Electrical Engineering or equivalent experience

• 8+ years of additional relevant work experience focused on computer architecture and SOC power-perf analysis and optimization.

• Understanding of the many factors influencing power efficiency at HW, SW, system, and product levels.

• Good understanding of HW-SW interactions for Deep learning, Multimedia, or Productivity use cases

• Strong interpersonal and teamwork skills.

• A drive to continuously learn and expand architectural breadth and depth.

Ways to stand out from the crowd:

• Experience with modeling and optimization of power and/or performance.

• Python scripting and SW programming

• Experience with prototyping power-optimization ideas on silicon

What you'll be doing:

• Invent and innovate low power architectural/RTL solutions and drive features and roadmaps for improving efficiency of our Desktop, Notebook and server platforms.

• You'll work cross functionally with other System/SW Architects, and Product engineers to understand energy efficiency improvements.

• Architect, Design and Verify features to help improve battery life and energy efficiency.

• Participate in architectural studies, tradeoff analysis, micro-architecture, and design, planning, verification, and validation efforts.

• Contribute to the development of techniques to develop highly accurate power and performance models for our GPUs, CPUs, Switches, and platforms.

• Drive performance vs power analysis to enable management/marketing with meaningful product decisions and customer interaction.

What we need to see:

• MSEE/MSCE (or equivalent experience) and 4 + years’ proven experience or PhD, with a specialization in Low Power Architectures or energy efficient design techniques is essential.

• Design experience with industry tools such as SystemVerilog RTL, UVM, Verdi, UPF, VCS NLP, Python, C++ are essential.

• Cross-discipline experience with understanding of HW/SW/System level interactions in important power efficiency scenarios.

• Solid understanding of advanced digital and analog circuits is highly desirable.

• Exposure to lab setup including power measurement equipment such as scope/DAQ. Your ability to analyze board-level power issues like supply voltage, over-current etc is helpful.

• Strong interpersonal and organizational skills and the ability & desire to work as a phenomenal teammate

Ways to stand out from the crowd:

• Background with HW/SW interactions

• Experience with Power what iffs and tradeoffs

• Experience in Clock tree power reduction and CG strategies.

• Background with RAM power optimization.

• Experience with directed and random functional testing including writing test plans and directed or random diagnostics.

What you'll be doing:

• Work with architects, designers, and performance engineers to develop an energy-efficient GPU.

• Identify key design features and workloads for building Machine Learning based unit power/energy models.

• Develop and own methodologies and workflows to train models using ML and/or statistical techniques.

• Improve the accuracy of trained models by using different model representations, objective functions, and learning algorithms.

• Develop methodologies to estimate data movement power/energy accurately.

• Correlate the predicted energy from models built at different stages of the design cycle, with the goal of bridging early estimates to silicon.

• Work with performance infrastructure teams to integrate power/energy models into their platforms to enable combined reporting of performance and power for various workloads.

• Develop tools to debug energy inefficiencies observed in various workloads run on silicon, RTL, and architectural simulators. Identify and suggest solutions to fix the energy inefficiencies.

• Prototype new architectural features, build an energy model for those new features, and analyze the system impact.

• Identify, suggest, and/or participate in studies for improving GPU perf/watt.

What we need to see:

• Pursuing or recently completed a MS or PhD in Electrical Engineering, Computer Engineering, Computer Scienceor equivalent experience.

• Strong coding skills, preferably in Python, C++.

• Background in machine learning, AI, and/or statistical modeling.

• Background in computer architecture and interest in energy-efficient GPU designs.

• Familiarity with Verilog and ASIC design principles is a plus.

• Ability to formulate and analyze algorithms, and comment on their runtime and memory complexities.

• Basic understanding of fundamental concepts of energy consumption, estimation, and low power design.

• Desire to bring quantitative decision-making and analytics to improve the energy efficiency of our products.

• Good verbal/written communication and interpersonal skills.

What You Will Be Doing:

• Bring new products and new technologies to high volume manufacturing

• Deliver datamation solutions for enhanced decision making

• Manage supplier performance evaluation matrix and keep it updated based on changing business needs

• Drive continuous improvement in manufacturing yield, cycle time and product quality/reliability

• Lead change control through qualification and notification

• Lead non-conforming material disposition

• Manage BOM supply chain and optimize sourcing solutions for best capacity and cost

What We Need To See:

• Master’s degree or higher in Engineering or Science with emphasis on Mechanical, Materials Science, Chemical Engineering fields (or equivalent experience)

• 12+ years of validated experience in Flip Chip semiconductor packaging design, process and materials development. Direct experience in advanced assembly technologies such as 2.5D/3D packaging, Photonics packaging experience is desirable

• Solid technical knowledge of materials, process, package design and equipment technologies in substrate, bumping, and chip assembly

• Strong skills in project management and supplier management

• Solid understanding of quality control, statistics process control, gage R&R and DOE techniques

• Good knowledge of packaging industry and its supply chain

• Excellent written and verbal communication skills

• Experience working with multi-functional teams across the world