דרושים Modelling Engineer ב-Arm ב-Sweden

As a hardware design engineer, you will make a difference by influencing the design methodology, taking ownership of complex work packages and driving them to success, including front-end implementation tasks like synthesis, logic equivalence check, power analysis and optimizations.

• An understanding of the entire ASIC/FPGA design flow and knowledge of hardware description languages: Verilog or System Verilog.
• Confirmed delivery record of high quality, low power, high performance sophisticated micro-architecture and RTL implementations in reasonable timescales.
• Skilled in planning design tasks and producing realistic effort and time estimates.

• Experience in working with requirements definition and management.
• Formal verification experience.
• Proficiency in developing C/C++ models of a microarchitecture.
• Familiarity with Arm architecture and AMBA bus protocols.
• Experience with CI platforms and version control tools.
• Practical knowledge of machine learning and neural networks.

This position can be either located in Lund (Sweden) or Cambridge(UK).

As a verification engineer, you will make a difference by influencing the verification strategy and methodology, taking ownership of complex work packages and driving them to success.

• Meticulous attention to detail, ensuring high-quality verification that minimizes bug escapes.
• Shown experience in block-level verification using UVM or similar methodologies.
• Strong knowledge of coverage driven verification for complex designs.
• Proficient in specifying, creating, and debugging SystemVerilog/UVM constrained-random testbenches.
• Skilled in planning verification tasks and producing realistic effort and time estimates.

• Experience in working with requirements definition and management.
• Formal verification experience.
• Proficiency in developing C/C++ models of a microarchitecture.
• Familiarity with Arm architecture and AMBA bus protocols.
• Experience with CI platforms and version control tools.
• Practical knowledge of machine learning and neural networks.

DDR Subsystem Architect is a technical role responsible for hardware architecture of LPDDR, DDR, HBM and GDDR subsystems for high-volume, sophisticated, SoC platforms on groundbreaking process nodes across multiple market segments including mobile, automotive, datacenter and networking, and IoT.

• Consume JEDEC specs and DRAM vendor roadmaps to create product intercept roadmaps.
• Work with SoC architects, business-units, and customers to establish & reconcile DDR subsystem features & requirements.
• Author architectural specifications to a mature stage allowing design and implementation teams to engage actively.
• Work with IP vendors to draft, negotiate, and execute SoWs/contracts.
• Work with design, verification, and validation teams to draft and review design specifications & test-plans (pre & post silicon), and support execution teams as required.
• Debug performance and functional issues with high-level models, RTL simulation, hard and soft IP.

• Deep understanding of DDR controller design and memory types (LPDDR, DDR, HBM, GDDR).
• Experience with controller-to-PHY interface protocols (DFI).
• Familiarity with Arm bus protocols such as APB, AXI, CHI, CXS, etc.
• Experience with performance/QoS, RAS, security, power-management, debug, and test features in the context of DDR subsystems.
• Bachelor's or Master’s degree in Electrical or Computer Engineering with minimum 10 years of experience in a senior development position.
• Excellent presentation, interpersonal, written, and verbal communication skills.

Arm is proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work collaboratively to defy ordinary and shape extraordinary!

• Partner and customer focus
• Collaboration and communication
• Creativity and innovation
• Team and personal development
• Impact and influence
• Deliver on your promises