Share
What you’ll be doing:
Develop verification infrastructure (testbenches, BFMs, checkers, monitors, randoms)
Come up with, review and drive test plan execution for planned features
Understand the performance requirements of your IP, come up with, review and drive performance testplan for your IP
Ensure code and functional coverage of all the RTL which you will verify.
Work with and enable FPGA and software teams to ensure that software is tested.
Plan for and be involved with post-silicon verification and debug.
What we need to see:
BS / MS or equivalent experience.
3+ years of ASIC verification experience of complex design units displaying good attention to detail, teamwork, problem solving and shown success
Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).
Background with System Verilog and UVM based methodology for ASIC verification.
Ways to stand out from the crowd:
Strong C/C++ programming experience
Prior Design or Verification experience of dynamic memory controllers (ddr{2, 3, 4, 5}, lpddr{2, 3,4,5, 6})
Strong debugging and problem solving skills.
Scripting knowledge (Python/Perl/shell).
Good interpersonal skills and ability & desire to work as a part of a team.
You will also be eligible for equity and .
These jobs might be a good fit