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Apple SoC Physical Design Engineer STA/Timing United States, California, Sunnyvale 283329216
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In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SoC using state of the art process technology.
- Minimum Bachelor's degree.
- Experience with STA.
- Experience with noise, crosstalk, and/or OCV effects.
- Familiar with important aspects of timing of large high-performance SoC designs in sub-micron technologies.
- Experience with STA and methodologies for timing closure.
- Familiar with circuit modeling, including SPICE models, and/pr worst-case corner selection.
- Good programming skills with Perl and TCL.
- Experience with large design STA and Timing Closure.
- Familiar with ECO techniques and implementation.
- Good communicator who can accurately describe issues and follow them through to completion.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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