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Apple Mixed-Signal Clocking Control RTL Design Engineer United States, California, Cupertino 279549328
03.04.2025
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In this role, you will be responsible for designing logic used to calibrate and control circuits such as oscillators, delay lines and phase interpolators. The logic design will involve working with multiple clocks, complex clock domain crossings, signal processing and control systems. You will need to analyze control loops for critical parameters such as gain, latency, transients and jitter. You will work closely with static timing experts for timing closure and front-end quality tools such as Lint/CDC/RDC. You will work with system architects to determine implementation of new designs, and with design verification teams to craft/debug tests. You will also contribute to post-silicon debug and analysis of these designs.
- MS degree in technical discipline with minimum of 3 years of relevant experience.
- Excellent knowledge of digital logic gates, clocking and state elements
- Excellent knowledge of writing synthesizable code in SystemVerilog
- Solid understanding of logic and behavioral simulations, and working knowledge of STA/Lint/CDC/RDC tools
- Solid understanding of clocking fundamentals such as jitter, phase and frequency modulation
- Good understanding of various phase and frequency detectors, oscillators, delays line and phase interpolators
- Prior experience working on clocking circuits such as PLLs/DLLs/CDRs
- Familiarity with DACs and oversampling modulators
- Familiarity with SERDES clocking and Equalization, line coding schemes and multi-level signaling
- Familiarity with the basics of digital signal processing and closed loop control
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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