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Apple RFIC Design Engineer 
United States, California, Sunnyvale 
997419356

06.06.2024
Description
As RFIC Design Engineer, you are going to be responsible for providing RFIC designs for wireless SoC and driving them to mass production for Apple’s Wireless Connectivity products. Responsibilities include:- Hands-on design contributions starting from concept, architecture, and topology to transistor-level feasibility studies, power, area, and performance trade-off analysis to actual design, simulations, and extractions. - Design and delivery of radio transceiver building blocks and chains including TX, RX, and PLL-LOGen for wireless connectivity products. - Work closely with RF Systems in block level and high level specifications of the TX, and RX line ups and PLL-LOGen, and proper distribution of spec margins in the chain. - Design of RF and Analog loopbacks for calibration and compensation. - Work through Co-Existence scenarios and design to meet the CoEx requirements. - Oversee the floorplan layout and verification of the design to ensure a successful tape-out. - Close collaboration with RFIC test engineers in the bring up, debug and optimization of the wireless connectivity chip through the productization.- Provide design versus silicon measurements correlation, and compliance with specification for a volume production.
Key Qualifications
  • RF/analog and mixed signal design experience in cutting-edge RF CMOS design.
  • Deep experience in designing and bringing into mass production of wireless transceivers is a plus.
  • Deep understanding of analog, mixed-signal and RF circuit design. This includes design of LNAs, and PAs, PLL/VCO/DCO/LOGEN blocks, mixers, baseband filters and amplifiers, data converters and calibration methods associated with such high performance wireless systems.
  • Deep understanding of analog design concepts such as analysis of noise, linearity, mismatch, stability, and other analog impairments.
  • Familiarity with various RF transceiver architectures and their trade-offs, system specifications and ability to work with system architects to translate system requirements into circuit requirements at IC level.
  • Understanding of impact of modulation type to radio architecture and requirements.
  • Demonstrated capability to work with digital design group for an optimum partition between digital and analog domain.
  • Familiarity with the integration flows and challenges of wireless SoCs.
  • Experienced in Cadence Virtuoso, Spectre RF, Matlab, EM simulation (EMX, HFSS) and similar tools.
  • Familiarity with mixed-signal mode verification methodology (SystemVerilog, AMS, Nanotime).
  • Experienced in Silicon characterization, and debug.
Education & Experience
BS and 3+ years of relevant industry experience. MSEE and PhD is preferred.
Additional Requirements
  • Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.
Pay & Benefits
  • At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $138,900 and $256,500, and your base pay will depend on your skills, qualifications, experience, and location.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
  • Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.