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Apple Physical Design Engineer United States, California, Cupertino 995983152
Today
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle. Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals. Perform timing, physical & electrical verification and drive the signoff closure for the partitions. Resolve design and flow issues related to physical design, identify potential solutions, and drive execution. Drive netlist to GDSII implementation for partition(s) meeting schedule and design goals. Work closely with the front-end/logic team to understand partition architecture and drive physical aspects early in the design cycle. Build partition level floor plan including pin placement, macro placement, and power grid. Perform block-level place and route and close the design to meet timing, area, and power constraints. Develop and validate high-performance low-power clock network guidelines. Generate and implement ECOs to fix timing using Static Timing Analysis (STA) through leakage and parasitic extraction. Improve signal integrity by reducing the effect of noise and resolving EM IR violations. Run the Physical design verification flow at the block level and fix LVS/DRC violations to meet the design requirements. Drive sign-off closure for the partition to meet design-specific requirements. Resolve design and flow issues related to physical design, identify potential solutions, and drive execution. Participate in establishing CAD and Physical Design Methodologies for correct by construction designs. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $143,100 - $214,500/yr and your base pay will depend on your skills, qualifications, experience, and location.
- Master’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering or related field.
- Experience and/or education must include:
- Experience with EDA tools for creating floorplans, placement and routing of multi-million transistors in the smallest footprint on Silicon.
- Clock and Power distribution networks.
- Experience designing with multi-corner & multi-mode scenarios to account for Silicon Process Voltage and Temperature (PVT) variations.
- Experience with static timing analysis to clean the design of setup and hold violations in circuits.
- Using scripting languages tcl and python to automate and mine trends and diagnostic data from experiments.
- Experience in design to mitigate effects of Electron Migration and experience in static and dynamic voltage drops to ensure functional Silicon.
- Understanding Design rule checkers to deliver a Tapeout clean database on time.
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