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Apple AMS SerDes Robustness Analysis & Validation Architect United States, California, Cupertino 99265252
19.05.2025
You will architect validation strategies that go beyond traditional spec-checking, focusing on uncovering weaknesses in design assumptions, stress-to-fail conditions, and system interactions across wide-ranging PVT and real-world scenarios, including edge case behaviors. A deep understanding of SerDes design and validation principles, SOC/system integration, and real-world system environments is required. In addition, you will also partner closely with the validation team to help optimize for maximum test coverage vs. execution time, ensuring efficient yet thorough validation. This is a hands-on lab role that requires strong collaboration with designers, architects, system, and test engineers to validate next-generation SerDes IPs from design conception through production and to ensure the IP is designed with design for testability.
- Define and architect margin-to-fail validation strategies to uncover weaknesses and failure conditions in high-speed SerDes PHYs across multiple process, voltage, temperature, and different system environments- Lead hands-on lab experiments to validate assumptions, isolate issues, root-cause failures, and fine-tune test coverage for both standalone IP and system-level interactions- Analyze silicon behaviors across multiple builds and revisions; derive insights to guide validation refinement and inform design updates- Provide post-silicon feedback that improves future architectural decisions, design margins, and validation methodology- Guide junior validation engineers, share debug techniques, and contribute to internal standard processes for SerDes validation
- BS and a minimum of 20 years relevant industry experience or equivalent
- 10+ years of experience in SerDes IP validation, AMS circuit design, or silicon/system-level debug
- PhD in Electrical Engineering or related field with 15+ years of experience in SerDes IP validation, AMS circuit design, or silicon/system-level debug
- Hands-on lab experience with lab instrumentations such as oscilloscopes, BERTs, protocol analyzers, etc, and
- measurement setups tailored for SerDes PHYs
- Deep understanding of high-speed serial link protocols (PCIe, USB, Ethernet, DisplayPort, etc.) and equalization techniques (such as CTLE, DFE, FFE etc)
- Strong foundation in analog/mixed-signal design principles and familiarity with signal integrity (SI) and power integrity (PI) impacts
- Skilled in programming (Python, C/C++, etc.) and data analysis tools for validation automation and correlation studies
- Proven track record to break down complex problems, isolate issues, and root-cause at the circuit, protocol, and system levels
- Demonstrated experience in design-for-validation, including fault injection, internal monitors, and behavioral hooks
- Experience validating multi-lane PHYs with adaptive EQ, clocking and CDR paths, and challenging compliance requirements in various real systems
- Familiarity with production and characterization flows, including margin-to-fail and stress testing techniques
- Ability to guide test coverage optimization to reduce execution time without sacrificing risk coverage
- Experience providing post-silicon insights that shaped future design changes
- Passion for deep debug and a “find the flaw” mentality, with an interest to explore the unexpected
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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