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Intel Defect Control Engineer Strong data analysis 
Ireland 
989568940

06.05.2024

Defect Control engineers' responsibilities include (but not limited to):

  • Collaborate with Technology Development team and Process Integration team members to import and setup new technology to production fabs.

  • Strong data analysis and programing skills - AI/Machine learning, Programming (SQL/Python/MATLAB), Software Development, Data Visualization.

  • Set up and optimize wafer inspection steps and recipes, to ensure detection of yield detracting defects in line at step.

  • Experience in Image process and big data analysis.

  • Work with Defect Metro engineers to optimize and identify the best inline defects detectability on the silicon wafers.

  • Execute and produce wafer inspection strategy to protect yield and quality at maximum productivity and lowest cost.

Candidate should possess the following behavioural skills:

  • Problem-solving technique with strong self-initiative and self-learning capabilities.

  • Ability to work with multi-functional, multi-cultural teams.

  • Must demonstrate solid written and verbal communication skills.

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

  • Bachelor's degree in science and engineering major.

  • Strong data analysis and programing skills:

  • Advanced programming and program-debug skills, Python being the ideal area of expertise,

  • AI/Machine learning, Programming (SQL/Python), Data Visualization

Preferred Qualifications:

  • Advanced degree (Master's or Ph.D.) in Physics or Materials Science major.

  • Hands-on experience in advanced node semiconductor industry in Defect engineering or Failure analysis.

  • 3+ years' experience with defect inspection tools in high-volume semiconductor manufacturing.

  • 3+ years' Hands-on experience in wafer inspection recipe setup and optimization.

  • 3+ years' experience with layout-sensitive defects and knowledge of scan diagnosis and other defect analysis skills.

  • Experience in new semiconductor technology development.

  • Basic understanding and collaboration experience with module processes including lithography, dry etch, wet etch, CMP, diffusion, implant, thin films and metrology.

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits