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Apple SoC Memory Performance Engineer Platform Architecture United States, New York, New York 984908891
06.06.2024
Description
- C++ performance modeling of proposed architectural solutions and features.- Gathering, analyzing, and validating measured and simulated results to compare architectural design alternatives.- Carefully analyze and present results to enable data specific architecture/design.- Measure and analyze existing SoC and workloads.- Some international travel is required for this position.
Key Qualifications
- Solid knowledge of cache management and memory controller for DRAM technologies. Prior experience on writing a cache and memory simulator using C++ is a big plus.
- Excellent C/C++/scripting coding, debug, and testing skills.
- Papers published in top computer architecture conferences/journals and filed patents related to computer architecture, demonstrating ability of designing and evaluating different cache and memory performance techniques
- Prior work on analyzing the memory access patterns and bandwidth/latency requirements of CPU, GPU, Video, Camera, Machine Learning hardware accelerators or similar areas.
- Expertise in cooperative code development using a revision control system such as GIT.
- Strong communication and documentation skills.
Education & Experience
BS and a minimum of 10 years relevant industry experience.
Additional Requirements
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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