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What You Can Expect
In-house Design, Simulation, and BOM Management.
Direct collaboration with TE/DE/SE teams within Marvell.
Enhance design accuracy before fabrication.
Shorten the design cycle time.
Standardize ATE Load Board Design Flow.
Develop templates and Best-Known Methods (BKM) for ATE load board design.
Source and manage critical, high-cost components.
Outsource fabrication and assembly to vendors with proven records of cost efficiency, fast cycle times, and consistent SI/PI performance, as well as high-quality fabrication and assembly standards.
What We're Looking For
3 to 10 years of experience as an Electrical Engineer specializing in high-speed IO design on complex, high-density printed circuit board assemblies for ATE applications, including ASIC, ODSP, CDSP, Switch, HDD, PreAmp, and Processors.
Extensive experience in managing ATE load board vendors and coordinating production timelines.
Deep understanding of Signal Integrity (SI) and Power Integrity (PI) design principles.
Skilled in simulation technologies, with hands-on proficiency.
Demonstrated ability to collaborate effectively with cross-functional teams, including test, design, verification, and product engineering.
Strong knowledge of mechanical and thermal components and their integration in ATE load board design.
Experienced with Cadence Allegro and Altium for schematic and layout design.
Excellent analytical and problem-solving abilities.
Bachelor’s degree in Electrical Engineering.
Expected Base Pay Range (USD)
115,790 - 173,500, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
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