Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
1 year of experience in RTL coding using Verilog or Systemverilog language.
Experience in one or more SoC Integration domains and flows (e.g., clocking or debug or fabrics/Network on Chip (NoC) or security or low power methodologies).
Preferred qualifications:
Experience with programming languages (e.g., Python, C/C++ or Perl).
Domain knowledge in one or more of these areas: process cores, interconnects, debug and trace, security, interrupts, clocks/reset, power/voltage domains, pin-muxing.