Microsoft Design Verification Engineer II 

United States, North Carolina, Raleigh 

971190049

Required Qualifications:

• 5+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience or internship experience.
• 3+ years of pre-silicon System on Chip (SOC), chip level, subsystem or IP verification experience.
• 3+ years of experience with verification principles, object-oriented programming, test plan development, testbench creation, stimulus generation, UVM/Open Verification Methodology (OVM), and coverage-based verification.
• 3+ years of experience in SystemVerilog, C/C++, and scripting languages such as Python, Ruby or Perl.

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

• Demonstrated experience on one or more of the following: Coherency, Caches, Fabrics, Double Data Rate (DDR) controllers, Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), Advanced eXtensible Interface(AXI)/Coherent Hub Interface(CHI) protocol bridges or other complex IP/blocks or subsystems.
• Experience with a full product cycle from definition to silicon, including writing IP/block or subsystem level test plans, developing tests, debugging failures and coverage signoff.
• Experience creating, maintaining, or integrating test benches, checkers and stimulus using System Verilog Test Bench (SVTB), Universal Verification Methodology (UVM), Formal Verification and/or C/C++.
• Experience in automating verification processes using Python or another scripting language.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until December 27, 2024.

• Establish yourself as an integral member of a pre-silicon verification and post-silicon validation team for the development of custom silicon components.
• Work with a team to write constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness.
• Develop Verification Intellectual Property (VIP) components to verify home grown designs.
• Develop Universal Verification Methodology (UVM) components to interface between test code and verification simulation environments.
• Define and implement functional coverage and drive coverage closure.
• Collaborate with Architecture, Design, Firmware/Software, Product Engineering, Program Management and third-party vendor teams to ensure pre-and-post-Si testing is comprehensive.
• Develop scripts for verification and validation infrastructure.
• Other
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