Microsoft Principal Logic Engineer 

United States, Oregon, Hillsboro 

965111382

Required Qualifications:

• 9+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.
• 8+ years of experience with Double Data Rate 4(DDR4) or Double Data Rate 5 (DDR5) Dynamic Random-Access Memory(DRAM) Memory Controller design.
• Knowledge of Joint Electron Device Engineering Council (JEDEC) DDR5 Specification.
• Fluency in Verilog and System Verilog and Dynamic Random-Access Memory Physical Layer ( DRAM PHY) and Interface Protocol(DFI) and High speed digital design experience.

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• Proficient with synthesis tools.
• Proficient with scripting tools.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until November 24, 2024.

• Microarchitect major blocks of a DRAM Memory Controller and implement the design with high quality in Verilog Register Transfer Level (RTL).
• Interface with PHY vendor.
• Work closely with front end design and physical design teams to ensure correctness of the Micro Controller(MC) design.
• Implement any additional required functional units in Verilog.
• Ensure high quality of the design from the perspectives of functionality, timing, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Logic Equivalence Check (LEC).
• Other
  • Embody our and