In this role, you will be: • Responsible for developing, improving, and maintaining the CDC and RDC sign-offs for CPU designs• Working with RTL and DV teams to recommend System Verilog assertions needed to support CDC/RDC/STA constraints and assumptions• Highlighting to the RTL team any CDC/RDC issues and recommending solutions to them and educating them on CDC/RDC issues and the importance of structurally safe solutions to each issue• Responsible for developing, enhancing, and maintaining key STA checks and associated sign-offs for our CPUs including things needed to complement CDC/RDC• Responsible for debugging vendor tool problems and collaborate with designers to help solve their problems• Working closely with EDA vendor representatives to drive improvements and new methodologies• Working closely with RTL, Verification, CAD, and Physical Design teams