Develops Electrical Test Plan and Automation Solution for memory systems margin validation.
Validates Memory IO circuit analog performance, electrical signal integrity compliance to industry standard specifications, and system level margin for stable operation and production target prediction.
Review Memory Training for validation and margin optimization. Validate, debugs, and optimizes memory training and circuit analog setting to improve margins and quality.
Conducts and participates in multidisciplinary research in the design, development, testing, validation, and utilization of memory IO and mixed signal architectures inclusive of industry standard datacom applications and custom Intel interfaces.
Provide platform board test requirement and design feedback.
Performs debug to identify root causes and resolves all functional and triage failures for electrical issues.
Defines Electrical Validation Strategy for memory IO interfaces to achieve optimized electrical performance and meet product production goals.
Own Electrical Validation risk assessment for each stepping of silicon tape out till Production Release Qualification.
Qualifications:
Min Qualification :
BS, MS degree in Electronic or Computer Science Engineering with at least 10 or more years of experience in related field
Strong problem-solving and analytical skills. Excellent communication and leadership abilities, capable of leading cross-functional debug efforts
Post-silicon system level hardware and software validation techniques and debug skills
Preferred Qualification:
Experience in Memory IP post silicon validation is a plus
Good understanding of DDR5, LPDDR5 memory topology, features and memory PHY circuit architectural analog design knowledge is a plus
Familiar with DRAM initialization, memory training and calibration process
Knowledge in memory analog tuning to improve system level margin
Possess hands on experience in post-silicon circuit electrical characterization activity, be it Bench Design Validation, Signal Integrity Validation, or System Margining Validation
Familiar with validation technique and electrical compliance requirement for high speed memory system
Familiar with DFT usage in Electrical Validation environment
Proficiency in operating hardware measurement equipment and tool, for example: BERT, oscilloscope, sigtest eye diagram tool and etc
Experience in C++, Python or any form of scripting for hardware access or automation