* Perform Sub system level floor planning, placement, and routing for high-performance microprocessor design.
* Collaborate with cross-functional teams to achieve design goals.
* Close the design to meet timing, power, and area requirements.
* Implement engineering change orders (ECOs) to rectify functional bugs and timing issues.
* Ensure the quality and efficiency of the RTL to GDS2 implementation process.
• 8+ years of industry experience
• Good knowledge and hands on experience in physical design , timing and methodology which include logic synthesis, placement, clock tree synthesis, routing , post route closure.
• Should be knowledgeable in physical verification ( LVS,DRC.. etc) ,Noise analysis, Power analysis and electro migration .
• Good knowledge and hands on experience in static timing analysis (closing timing at chip level)
• good understanding of timing constraints .
• Should have experience in handling asynchronous timing, multiple corner timing closure.
- Automation skills in PYTHON, PERL ,SKILL and/or TCL
