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Apple CPU Design Timing Engineer United States, California 93464485
14.04.2025
In this role, you will be responsible for all aspects of timing including working with the implementation and RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and timing closure.
As the CPU Design Timing Engineer, you will be responsible for the timing closure of the project. Responsibilities include but are not limited to:• Working with the CAD team to develop the timing flow that will be used on the project including scripting to improve analysis flows and engineer efficiency.• Work extensively with CPU micro-architects and Implementation engineers to drive timing closure for the CPU.
- Minimum BS and 3+ years of relevant experience
- Understanding of Static Timing Analysis Fundamentals
- Experience with noise analysis and fixing noise in designs
- Experience with variation modeling in static timing analysis tools
- Experience with TCL and either Perl or Python
- Must possess data parsing, analysis, and representation/plotting skills
- Prior experience performing timing analysis in high speed digital designs such as CPUs or other similar designs
- Experience in a static timing analysis tool such as PrimeTime®/Tempus®
- Knowledge of physical design tools and methodology including logic synthesis, PnR, parasitic extraction, and logic equivalence
- Understanding of deep sub-micron technologies and scaling trends
- Working knowledge of CPU microarchitecture
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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