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Google Formal Verification Engineer Subsytem Silicon 
India, Karnataka, Bengaluru 
934400887

Yesterday
Minimum qualifications:
  • Bachelor's degree in Mechanical Engineering, Electrical Engineering, Industrial Engineering or equivalent practical experience.
  • Experience in formal verification applications (e.g., sequential equivalence checking, and connectivity checking) and data-path verification.
  • Experience with formal sign-offs of industry ASIC designs.
  • Experience with scripting languages (e.g., Python/Perl, and TCL).
  • Experience with formal methodologies and abstraction techniques.

Preferred qualifications:
  • Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or equivalent practical experience.
  • 5 years of experience with SystemVerilog and SystemVerilog Assertion.
  • Experience with formal verification, Formal Property Verification, different complexity reduction techniques and different abstractions.