Microsoft Senior Analog Computer Aided Design CAD Engineer 

United States, North Carolina, Raleigh 

932970567

The Microsoft Silicon, Cloud Hardware, and Infrastructureorganisationseeking anengineer to join our Central Analog Computer-Aided Desing (CAD) Tools, Flows and Methodology (TFM) group leading physical verification across a multitude of technology nodes. This team drivesstate-of-the-artconverged solutions, automation, and quality assurance checks across theanalogand custom digital design domain from schematic entry through tape-out.  This team supportsnumeroussimultaneous projects within Microsoft by developing workflows for our design engineers so that they can deliversilicon solutions for Microsoft.

to join our team!

Required Qualifications:

7+ years of related technical engineering experience

o OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience

o OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience

o OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

3+ years of experience with physical verification tools such as Siemens, Cadence Pegasus/PVS, Synopsys ICV or similar.

3+ years of experience usingLinux for day-to-day activitiesin a professional or personal

3+ years of experience collaborating with a broad group of engineers to solve challenging problems.

Other Requirements:

to meet Microsoft, customer and/or government security screening requirementsfor this role. These requirements include but are not limited to the following specialized security screenings:

Microsoft Cloud Background Check: This position will beto pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Qualifications:

• MS in Electrical Engineering, Computer Engineering, ComputerScienceor equivalent work experience

• 10+ years of relevant experience
• 7+ years of experience in analog/custom IP design and/or CAD tool developmentin thephysical verificationdomain

• Understanding of object-oriented programming in languages such as Python or Ruby

• Experience with git and continuous integration systems

• In-depth experience writing custom DRC and LVS decks

• In-depth experience with PERC debug and analysis

• Familiarity with SKILL programming language for use in Virtuoso

• Familiarity with layout construction in Cadence Virtuoso and/or Synopsys Custom Compiler in Advanced Nodes

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $117,200 - $229,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $153,600 - $250,200 per year.Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:Microsoft will accept applications for the role until Aug 15, 2024.

#azurehwjobs #SCHIE

• Collaborate with the central CAD organization as well as across design teams to align roadmap for physical verification needs for custom IP as developed for Microsoft Silicon projects.

• Maintain internal tooling used by design teams to execute physical verification tasks including LVS, DRC, ERC, and PERC.

• Provide guidance andexpertiseto design teams when assessing new rules or debugging errors.

• Audit physical verification settings to ensure alignment with internal customers and foundry partners.

• Proactively engage with Electronic Design Automation (EDA) vendors tooptimizeflows with the latestcutting-edgetechnology.

• Develop andmaintainregression and test cases to exercise updates to rule decks and tool versions.

• opportunities for custom rule decks that enhance physical verification beyond vendor-provided flows.

Embody our and