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Apple Design Verification Engineer United States, Texas, Austin 923068076
18.11.2024
Description
* You will collaborate with all disciplines (vertical product model) * You will ensure the quality of the SC or a IP or subsystem * You will review design and architecture specifications and work closely with micro-architecture teams * You will understand the functional & performance goals of the design and you use this knowledge to test effectively * You will develop test plans, tests and coverage plans as well as define Apples next generation verification methodology test benches * You will communicate and collaborate with design, architecture and software teams to understand the use cases and corner conditions and drive test cases * You will run and triage regressions, tracking bugs, and analyzing coverage to achieve top results
Minimum Qualifications
- * Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy
- * Knowledge of Verilog/System Verilog, digital simulation and debug
- * Knowledge of computer architecture and digital design fundamentals
- * Ability to work independently to deliver the project goals
- * Exposure to UVM is desired
- * Experience with C/C++, assembly is a plus
- * Experience with Perl, Python, or similar scripting language
- * Strong problem solving and analytical skills
- * Strong communication skills combined with team-oriented approaches to own the verification efforts
Preferred Qualifications
- BSEE or BSCS required, Master’s or PhD desired
Additional Requirements
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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