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As a Design Verification manager, you will lead a team of ASIC design verification engineers to verify IP and Subsystems that be integrated into multiple ASICs that are integral to the Kuiper Communication link. The team will verify communications level signal processing IP and sub-systems. These products will span terrestrial and in space usage. You will work closely with SoC Architects, software and design teams to verify that IP meets the power, performance and area goals for Kuiper. You will lead a team defining the processes, methods and tools for design verification of large complex IP blocks and subsystems.Key job responsibilities
In this role you will:- Define and own IP through ASIC DV development methodologies
- Act as a technical point of contact to the different IP and SoC design teamsExport Control Requirement:
- BS degree or higher in Electrical or Computer Engineering
- 10+ years or more of practical semiconductor ASIC DV experience including owning end-to-end verification of major SoC blocks
- 3+ years’ experience managing a team of engineers, including including hiring, scheduling and budgeting
- Successful tape outs as an owner of a major design block
- Familiarity in developing wired/wireless communication chips
- Experience in verifying Modem IPs at block-level and full chip level.
- Experience in understanding models written in Matlab, C/C++, and SystemC
- Experience building test plans, test benches and advanced verification practices
- Proficient in design methodologies and EDA tools
- Familiarity with low power design using UPF flow
- SoC bring-up and post silicon validation experience
- Experience with hardware-assisted verification, emulation, or/and FPGA prototyping
- Experience working with RTL simulation, synthesis and low-power design
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