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Apple Emulation Verification Engineer 
United States, California, Sunnyvale 
884973279

Yesterday
As a member of Emulation verification team, you will play a key role in using Emulation for verification of large Wireless SoCs. You will also be involved in the most cutting-edge technology of bringing in mixed signal models onto the Palladium platform. The overall work will involve porting the design onto the Palladium platform, followed by executing the detailed Emulation test plan.• Work closely with the emulation team to bring up large Wireless SoCs along with their mixed-signal components in the emulation platform.• Develop monitors and checkers on the emulation platform.• Prepare and execute the test plan and perform reviews with the cross-functional teams.• Collaborate cross-functionally with Design, Architecture, Power, Silicon Validation, Performance, and SW Teams.•Develop code for Design and verification that aids with emulation activities, using Verilog/System Verilog/UVM.
  • BS and 3 years relevant industry experience.
  • Experience with System Verilog, Verilog or UVM.
  • MS and 3+ years of industry experience with bring-up, debugging, and verification in Emulation.
  • Knowledge of tool flow from RTL to Emulation is a big plus.
  • Proven Design Verification or Silicon Validation skills.
  • Experience in writing Synthesizable System Verilog/Verilog code and System Verilog assertions.
  • Experience with any Scripting (Perl/Python/TCL).
  • Excellent analytical and debug skills.
  • Good understanding of any Standard Emulator (Palladium, Veloce, Zebu) or FPGA (Xilinx, Altera) flow.
  • Experience with System Verilog verification environments including C/C++ DPI, UVM.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.