In this role, you will be responsible for writing functional models of custom mixed-signal circuits in SystemVerilog with the right amount of detail, while also incorporating non-idealities. You will collaborate with circuit design teams to understand details of custom circuits, and with DV teams to craft hooks into the models for effective verification. You will analyze data provided by the circuit team in Python/MATLAB for fitting into the model and analyze the performance of the resulting model by profiling. You will run simulations and formal equivalence tools to ensure that the model matches closely with the custom circuits. You will work with other experts in this domain to enhance modeling methodology, improve functional coverage, optimize modeling flows and enable new tools to identify custom circuit issues.