Nvidia Senior SRAM Circuit Design Engineer 

United States, California 

881655508

Program Management: Evaluate and explore the inner workings of foundry models and CAD tools, maintain testcases, automate PDK evaluation, and publish benchmarks

Data Analysis: Extensive model-vs-silicon data analysis, exploring device and wire models, as well as higher-level SRAM bitcell issues like Vmin, Vmax, and Iread

Product Guidance: Collaborate with architecture, RTL, place & route, DFT, CAD, circuit design, yield operations, and even external foundries to provide guidance and data analysis on RAM design issues, such as silicon bringup/yield, architectural planning, redundancy/repair, testing, low-voltage operation, and DRC/DFM impact

Circuit Design: Transistor-level circuit design, layout implementation, physical and logical verification, and debug of SRAM macros and test structures for early test vehicles on advanced processes, focusing on design for testing and yield analysis

Looking Ahead: Evaluate existing and pursue new memory design trends for applicability to future NVIDIA products and processes

BSEE minimum or equivalent experience, MSEE or PhD preferred

10+ years of SRAM design experience with strong background in layout, process understanding, and DRC rules on advanced FinFET processes

Prior design experience in single-port, dual-port, multi-port, or register file SRAM-based macros required, including complex circuits like self-timed logic and senseamps

Scripting ability to parse data and automate tasks

Successful track record of delivering designs to production

Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role

Expertise with Vmin/Vmax assist techniques

Foundry interface and program management skills

Familiarity with Cadence SKILL

Lab testing/debug experience